傳統上，晶片皆切割成相同高度的列，並由與列同高的標準電路元件組成。相較於高度較矮的標準電路元件，高度較高的標準元件能提供較好的效能，但也有著較大的面積以及功耗代價。為了達到面積以及效能之間的平衡，我們提出混合列高度元件的晶片設計，其中每個標準元件有著不同高度的版本的選擇。同時，依據標準元件的效能需求，我們會選擇選擇其較高或較矮高度的標準元件。例如，位於關鍵路徑上的標準電路元件，為了因應其較高的效能需求，會傾向使用高度較大的標準電路元件來提高效能。反之，對於不在關鍵路徑上的標準電路元件，會傾向使用高度較小的標準電路元件，以避免額外的面積和功效耗費。在先進製程中，全域擺置是以減少電路元件之間連線長度及擁擠度等為目標，初步決定每一個電路元件在晶片中大致上的位置。然而現今學術界的全域擺置工具當中，皆是以等列高元件擺置的流程為主，目前尚未有學術界的全域擺置工具實現混合列高度元件的擺置。因此在本篇論文中，我們利用了現有學術界中僅能處理等列高元件擺置的全域擺置工具，開發了一套可以實現混合列高度元件的全域擺置的流程。實驗結果顯示，在合理的時間範圍內我們可以解決現有等高擺置工具處理混合高度元件時產生的擁擠問題，並使電路元件之間連線長度進一步縮小。

Traditionally, a uniform-row-height design is divided into uniform-height rows and consists of standard cells, whose heights are the same as rows. Compared with cells with the shorter height, cells with the taller height can drive cells better and promote the performance. However, they induce more power consumption and larger cell areas, which result in an unwanted larger die area. To achieve the trade-off between die area and performance, we provide mixed-row-height design, where each standard cell has taller version and short version. Meanwhile, standard cells choose their versions according to the design need. For example, standard cells on critical paths require a higher driving ability to achieve the performance requirement. Accordingly, they adopt tall versions. In contrast, there is no need to promote the driving ability for standard cells away from critical paths. Hence, they choose short versions to save the area. Moreover, we divide a fixed die into interleaving tall rows and short rows for cells with either taller or shorter height to place. In the modern physical design flow of VLSI circuits, global placement will decide a rough position of each standard cell while optimizing objectives such as wirelength and local density overflow. However, there is no existing global placement tool that is capable of dealing with such mixed-row-height design. Thus, in this thesis, we propose a mixed-row-height global placement flow leveraging current academic global placement tools that can only handle uniform-row-height designs. The experimental results show that our proposed flow is able to minimize wirelength and local density overflow in both short-row regions and tall-row regions.

Acknowledgements
摘要i
Abstract ii
1 Introduction 1
2 Problem Formulation and Overview of Our Proposed Algorithm 6
2.1 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Overview of our proposed algorithm . . . . . . . . . . . . . . . . . . . . . . . 8
3 Proposed Algorithm 10
3.1 Initial placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Cell-shape transformation into uniform height . . . . . . . . . . . . . . 10
3.1.2 Uniform-row-height global placement . . . . . . . . . . . . . . . . . . 11
3.1.3 Cell-shape restoration . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.4 Version change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Placement refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Analytical refinement model . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Overflow mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Cell alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Experimental Results 26
4.1 Effects of placement refinement stage . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Effectiveness of each step in the placement refinement stage . . . . . . . . . . 29
4.3 Runtime analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4 Remark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Conclusion 34
References 35

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