本論文為操作在35GHz具有三角積分調變器的鎖相迴路，其中的電路有參考信號預除器、相位檢測器、充電泵、迴路濾波器、可選頻帶之LC壓控振盪器、除頻器、三角積分調變器，其中加入了OP來改善電路中的不理想效應，並運用切換是電容層降低單一頻帶壓控振盪器的增益來提升相位雜訊的表現，此外，為了面積的考量，在除頻器的部分我所使用的是電流模式除頻器而不是注入式鎖定除頻器，原因是因為面積考量。此論文採用台積電所提供65奈米CMOS製程進行模擬設計，論文包含了介紹鎖相迴路中各個子電路的數學模式，設計方式，不理想效益之解決方法，最後對鎖相迴路做全面性的結論。

This paper is a phase-locked loop with a delta-sigma modulator operating at 35GHz. The circuit includes a reference signal pre-divider, phase detector, charge pump, loop filter, LC voltage controlled oscillator with selectable frequency band, frequency division. And delta-sigma modulators, in which OP is added to improve the undesired effect in the circuit, and switching is used to reduce the gain of the single-band voltage-controlled oscillator to improve the performance of phase noise. In addition, for area considerations In the frequency divider part, I use the current mode frequency divider instead of the injection-locked frequency divider because of the area consideration.This paper uses the 65nm CMOS process provided by TSMC to carry out simulation design. The paper includes the mathematical mode of each sub-circuit in the phase-locked loop, design methods, and solutions to unsatisfactory benefits. Finally, a comprehensive conclusion is made on the phase-locked loop .

摘要................................................................................................2
Abstract..........................................................................................2
目錄................................................................................................4
圖目錄.............................................................................................6
表目錄.............................................................................................9
第一章 緒論....................................................................................10
1.1研究動機.........................................................................10
1.2論文章節介紹...................................................................10
第二章 鎖相迴路基本原理與架構介紹...................................................11
2.1鎖相迴路介紹...................................................................11
2.2鎖相迴路基本子電路介紹....................................................12
2.2.1相位/頻率檢測器...............................................12
2.2.2充電泵.............................................................16
2.2.3迴路濾波器.......................................................21
2.2.4電壓控制振盪器.................................................24
2.2.5除頻器.............................................................49
第三章 鎖相迴路之系統分析...............................................................54
3.1鎖相迴路的相位雜訊..........................................................54
3.2鎖相迴路的穩定性分析.......................................................57
第四章 35G赫茲鎖相迴路之電路實現....................................................68
4.1參考頻率預除器............................................................... 68
4.2相位頻率檢測器................................................................69
4.3充電泵............................................................................73
4.4迴路濾波器......................................................................75
4.5電壓控制振盪器................................................................77
4.6除頻器............................................................................83
4.7三角積分調變器................................................................85
第五章 模擬結果..............................................................................92
5.1參考頻率預除器..............................................................92
5.2相位頻率比較.................................................................93
5.3充電泵..........................................................................95
5.4壓控振盪器操作頻帶與相位雜訊.........................................97
5.5 CML波形輸出.................................................................99
5.6三角積分調變器.............................................................100
5.7迴路模擬..................................................................... 101
第六章 結論..................................................................................102
6.1總結........................................................................... 102
6.2參考文獻..................................................................... 102

[1]蕭介勛.(2008)本地振盪源的注入鎖定與牽引現象研究(Doctoral dissertation,撰者)
[2]陳偉存.(2017).一個操作在2.8-4.8GHz的三角積分鎖相迴路.清華大學電機工程學系研究所論文.
[3]劉深淵，楊清淵，<鎖相迴路>。滄海書局，2017
[4]高曜煌，<射頻鎖相迴路IC設計>。滄海書局，2017
[5]張玉澔.(2018).操作在三百五十億赫茲具有三角積分調變器的數位式鎖相迴路.清華大學電機工程學系研究所論文.
[6]Lee, J., &Wang, H.(2009).Study of subharmonically injection-locked PLLs.IEEE Journal of Solid-state Circuits,44(5),1539-1553.
[7]Razavi,B.(2004).A study of injection locking and pulling in oscillators. IEEE journal of solid-sstate circuits,39(9),1415-1424.
[8]Imani, A, &Hashemi, H.(2017). Distributed Injection-locked Frequency Dividers. IEEE Journal of Solid-State Circuits,52(8),2083-2093.
[9]Rategh, H. R,&Lee,T.H.(1999).Superharmonic injection-locked frequency dividers.IEEE Journal of Solid-state Circuits,34(6),813-821.
[10]Lee,J.,Li,Y.A.,Hung,M.H.,&Huang,S.J.(2010).A fully-integrated 77-GHz FMCW radar transceiver in 65-nm CMOS technology. IEEE Journal of Solid-State Circuits,45(12),2746-2756.
[11]Kuo,Y.H,Tsai,J.H.,Chou,W.H,&Huang,T.W.(2010,December).Admittance-transforming injection-locked frequency divider and low-supply-voltage current mode logic divider.In Microwave Conference Proceedings(APMC),2010 Asia-Pacific(pp.782-785). IEEE.