近年來，為了改善人工智慧運算的表現與能源效率，研究人員探索了由憶阻器建構的深度神經網路與脈衝神經網路架構。然而，憶阻器元件容易受到製程偏移及缺陷的影響，這會導致系統中的各種錯誤和故障。在本篇論文中，我們提出了一種基於憶阻器的脈衝神經網路測試方法。首先，我們對脈衝神經網路硬體進行電路層級模擬，過程中我們考慮了製程偏移對電路的影響，並分別加入所有憶阻器陣列中可能發生的開路與短路缺陷及憶阻器錯誤，並將模擬結果與無缺陷電路比較。我們從分析結果得出所加入的缺陷與錯誤可以被簡單地分成二個錯誤模型，也就是慢積分錯誤與快積分錯誤。我們也基於脈衝神經網路硬體開發了一個錯誤模擬器，可用於模擬硬體中的缺陷與錯誤，以及模擬我們提出的March-SNN測試演算法。在March-SNN演算法中，透過輸入指定的測試型樣 (輸入脈衝) 並觀察輸出的測試回應 (輸出脈衝) 來進行測試。由於March-SNN是使用脈衝神經網路電路中的現有操作來進行測試，因此能夠減少額外的硬體成本。實驗結果表明，March-SNN能夠100%覆蓋我們提出的缺陷與錯誤模型。

Memristor-based computing architectures for deep neural network (DNN) and spiking neural network (SNN) have been explored in recent years, for improving the performance and energy efficiency of AI computing. However, memristor cells are susceptible to manufacturing defects and process variations, which will result in various faults and failures in the system. In this thesis, we propose a test method for memristor-based SNN hardware. We first perform circuit-level simulations of the SNN hardware, taking process variations into account. All feasible open and short defects and the memristor program fault are respectively injected and compared with the fault-free circuit. From the analysis result, we conclude that the injected defects and faults can be covered by two simple fault models, i.e., the Slow Integration Fault (SIF) and Fast Integration Fault (FIF). We also develop a fault simulator that can be used to simulate March-like test algorithms for the proposed defects and fault models, based on the memristor-based SNN circuit. We propose a March-like test algorithm, called March-SNN. Testing is done by applying the specified input test patterns (input spikes) according to the algorithm and observing the output test responses (output spikes), with existing operations of the SNN circuit to reduce additional hardware overhead. Experimental results show that March-SNN covers 100% of the proposed defects and fault models.

摘要 i
Abstract ii
Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Related Works 2
1.3 Proposed Method and Results 3
1.4 Thesis Organization 4
Chapter 2 Background 6
2.1 Introduction to Memristor Array and Operation 6
2.1.1 Memristor Resistive Switching Mechanism 6
2.1.2 Memristor State 7
2.1.3 Memristor Array 8
2.2 Introduction to Spiking Neural Network 9
2.3 Memristor-Based Spiking Neural Network 10
Chapter 3 Proposed Defect and Fault Models 15
3.1 Fault-Free Behavior 15
3.2 Defects and Fault Models 17
3.2.1 Open Defects 18
3.2.2 Short Defects 19
3.2.3 Memristor Faults 20
3.2.4 Transistor Faults 21
3.3 Simulation Results 22
3.4 Slow Integration Fault Model 24
3.5 Fast Integration Fault Model 25
Chapter 4 Proposed Test Algorithm and Spiking Neural Network Fault Simulator 27
4.1 SNN Fault Simulator 27
4.1.1 Input Pattern and Memristor State Array 29
4.1.2 Memristor and Transistor Variation Injection 30
4.1.3 Fault Injection 33
4.1.4 Output Response 33
4.2 Proposed Test Algorithm 35
Chapter 5 Experimental Results 43
5.1 Experimental Settings 43
5.2 Test Algorithms and Fault coverage 44
5.3 Discussion 47
Chapter 6 Conclusion and Future Work 50
6.1 Conclusion 50
6.2 Future Work 50
Bibliography 52

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