本論文呈獻了兩種生成正交時脈信號的方法，此信號應用於時序交錯式5-GS/s取樣系統。為了提供可擴展的取樣頻率，兩個時脈產生器的操作頻率可以由150MHz至1.25GHz進行廣泛調整。提出的第一個實現方式基於除頻器，因數位的特性而具有降低電路複雜性和面積佔用的優勢。此外，採用同步的重置訊號確保所需的輸出相位順序。論文中更強調第二種實現方式，使用鎖相迴路以達到較寬的操作範圍。透過自偏壓技術，鎖相迴路自我調整其頻寬，從而產生隨著參考時脈縮放的固定迴路動態。此外，我們也描述了幾種用於減小正交相位誤差的時脈分配技術。
使用90奈米互補式金氧半導體製程，量測顯示壓控振盪器表現出從20MHz至1130MHz的98%頻率可調範圍，且鎖相迴路在1.25GHz輸出頻率下的方均根抖動為3.3ps，而峰對峰抖動為33.6ps。使用625MHz參考輸入，相位雜訊於偏置頻率1MHz處測得為-115dBc/Hz。晶片於1伏特供壓下消耗4毫瓦，核心面積佔約0.016平方毫米。

This thesis presents two approaches for generating quadrature clock signals applied to a time-interleaved 5-GS/s sampling system. To offer a scalable sampling rate, the operating frequency of both clock generators can be widely tuned from 150 MHz to 1.25 GHz. Based on a frequency divider, the first proposed implementation has the advantage of reducing the circuit complexity and area occupation due to its digital nature. In addition, a synchronous reset is employed to ensure the desired output phase sequence. The second implementation, on which we put more emphasis, achieves a wide operating range by using a phase-locked loop (PLL). With self-biased techniques, the PLL adaptively adjusts its bandwidth, thus producing constant loop dynamics that scale with the reference clock. Furthermore, we describe several clock distribution techniques to minimize quadrature phase error.
Fabricated in a 90-nm CMOS process, measurement results show that the VCO exhibits a tuning range of 98% from 20 MHz to 1130 MHz, and the PLL achieves a RMS jitter of 3.3 ps and a peak-to-peak jitter of 33.6 ps at 1.25 GHz output frequency. With a 625-MHz input reference, the phase noise is measured to be -115 dBc/Hz at 1-MHz offset. It consumes 4 mW from a 1-V supply and occupies an active area of about 0.016 mm2.

Contents i
List of Tables iii
List of Figures iv
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Implementation of Divider-Based Quadrature Clock Generator 4
2.1 Quadrature Divider . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Design of Synchronous Reset . . . . . . . . . . . . . . . . . . . . 6
2.3 Differential Clock Buffers . . . . . . . . . . . . . . . . . . . . . . 9
3 Implementation of PLL-Based Quadrature Clock Generator 12
3.1 Analysis of PLL Linear Model . . . . . . . . . . . . . . . . . . . . 13
3.2 Fundamentals of Self-Biased PLLs . . . . . . . . . . . . . . . . . 19
iCONTENTS
3.3 PLL Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Phase Frequency Detector . . . . . . . . . . . . . . . . . . 23
3.3.2 Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . 25
3.3.3 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.5 Edge-Combining Clock Encoder . . . . . . . . . . . . . . 40
3.4 PLL Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 41
3.5 PLL Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Clock Distribution 53
5 Measurement Results 55
5.1 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 PLL Measurement Results . . . . . . . . . . . . . . . . . . . . . . 58
5.2.1 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2.2 Free-Running VCO . . . . . . . . . . . . . . . . . . . . . . 60
5.2.3 Closed-Loop PLL . . . . . . . . . . . . . . . . . . . . . . . 61
6 Conclusion 66
Bibliography 67

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