目前非揮發性記憶體的發展在記憶體市場上具有龐大的潛力，現今以快閃記憶體為最大宗，然而快閃記憶體需要在高電壓下才能進行寫入和抹除資料，且操作速度較慢並且難以隨著先進製程一直微縮。因此，下世代新型的非揮發性記憶體如STT-MRAM，ReRAM等，可以在低電壓下操作且有百倍以上的操作速度，成為了取代快閃記憶體的選擇並應用在各式各樣需要高速運算的終端裝置上。
而現今許多終端設備與機器上，對於資料安全防護的意識與需求越來越高，這些裝置多數使用安全散列算法（SHA）或進階加密標準（AES）演算法將內部的資料以及明文進行數據加密。而這些操作需要高速的讀取速度和可以搭配wide-IO的非揮發性記憶體（NVM）來實現高讀取帶寬。此外，為了減少傳統馮紐曼(Von Neumann)架構運算中大量的資料搬移，在記憶體內放置運算單元的近記憶體運算 (Near memory computing)可以有效降低安全相關演算法的運算時間以及功耗。
自旋力矩轉移-磁阻式隨機存取記憶體（STT-MRAM）是主要用於先進製程節點的on-chip非揮發性記憶體，有著現在非揮發性記憶體中最快的讀取速度。但是，它需要具備小偏移量的感測放大器才能容忍微小的穿隧式磁阻比例(TMR-Ratio)來進行穩定的讀取，會造成大量的面積消耗和讀取能量（ERD）。因此設計一個高讀取帶寬、安全相關自旋力矩轉移-磁阻式隨機存取記憶體運算巨集主要面臨的挑戰有：
1. 使用大量的感測放大器進行平行讀取，可實現較短的讀取時間，但會導致峰值電流（IPEAK）提高和消耗大量面積和能量。若使用較少數目的感測放大器依序讀取多位元可減少高峰值電流和面積及能量消耗，但會導致較長的讀取時間進而降低讀取帶寬。
2. 具有較高峰值電流的自旋力矩轉移-磁阻式隨機存取記憶體巨集會降低晶片的電源穩定性，可能會導致同一晶片上對雜訊敏感的區塊出現故障。
3. 傳統的記憶體-邏輯單元分離架構於非揮發性記憶體的安全邏輯運算會導致較長的延遲時間 (wide-IO讀取及觸發器做移位/旋轉位元需要兩個週期)，以及消耗額外的面積跟能量。
本論文主要討論自旋力矩轉移-磁阻式隨機存取記憶體在高帶寬讀取中的出現的問題，以及傳統馮紐曼架構的效能瓶頸，並提出結合了低能耗多位元電流感測放大器（LEMB-CSA）以及高面積效率近記憶體運算之電路。放大器具有電流裕度持續增強、製程變異容忍、小面積、低峰值電流、低能耗的特性；而內嵌於感測放大器之下的近記憶體運算電路具有高面積效率以及低功耗的表現，有效解決了前面所提到的設計挑戰。
在台積電22 奈米製程分析下，我們提出的讀取架構相較於傳統電流感測放大器可有35.2%的良率改善且多容忍80%的穿隧式磁阻比例。此外，減少的參考電流數量和流水線電流採樣方式使我們提出的感測放大器的能耗相較於2020年ISSCC發表的多位元電流感測放大器減少了36.4％，峰值電流降低了40％，可容忍之偏移量提升1.3倍，而僅付出相對於傳統電流感測放大器(並行感測) 18.2％讀取速度的代價。而我們提出的近記憶體運算電路可以減少33.3%的面積消耗和48.8%的功耗，並可以結合電流感測放大器的讀取操作，在一個工作週期內完成移位/旋轉位元的邏輯運算。
最後，我們與台積電合作在22奈米以及28奈米的CMOS工藝中實做並驗證我們提出的架構，本篇的量測驗證以28奈米的記憶體測試巨集為主，在VDD = 0.9伏特時，8個位元的讀取速度 = 3.12奈秒(ns)，而在感測8位元+完成1位元移位/旋轉的近記憶體運算模式中為3.29奈秒(ns)，僅額外多消耗了0.17奈秒(ns)。

The development of non-volatile memory (NVM) has great potential on storage memory market now, especially for the flash memory. However, the flash memory requires high voltage to program and erase data, low operation speed and it is hard to scaling down in the advance technology node. So the emerging non-volatile memory such as STT-MRAM, ReRAM which can operate in low supply voltage and achieve hundred times of operation speed become the choice to replace flash memory, and used in many kinds of edge devices that require to compute in high speed.
The awareness and requirement of data protection are increasingly concerned in many edge devices and machines. Most of these applications use Secure Hash Algorithm (SHA) or Advanced Encryption Standard (AES) functions for data/plaintext encryption, and they require high read speed and non-volatile memory (NVM) that can be used with wide-IO to achieve high read bandwidth. Besides, to reduce the large amount of data movement in typical Von Neumann architecture, near-memory-computing can decrease the security-related algorithms latency and power consumption efficiently.
Spin Torque Transfer-Magnetoresistive Random Access Memory (STT-MRAM) is the major on-chip NVM for advanced process nodes, it has the fastest read speed in the recent NVMs; however, it requires small-offset sense amplifiers (SAs) for robust read against small TMR-ratio at the expense of large area overhead and read-energy (ERD). Therefore, design a high bandwidth STT-MRAM macro for security-related applications imposes the following challenges:
1. Using a large number of SAs for parallel readout to achieve short TAC, but results in high peak current (IPEAK) and large area overhead. Using fewer SAs for sequential readout reduces IPEAK and area overhead, but imposes long TAC and decreases read-bandwidth (BWR).
2. MRAM macros with high IPEAK degrade the supply (VDD) integrity of the chip, often leading to failure in noise-sensitive blocks on the same chip.
3. A conventional memory-logic-separated scheme imposes a long latency (2 cycles: wide-IO memory read + flip-flop (FF) shift/rotate), extra area overhead, and power consumption for NVM-based security logic operations.
In this thesis, we mainly discuss the issues in high bandwidth reading with STT-MRAM, and the performance bottleneck in typical Von Neumann architecture. Then we propose a low energy multi-bit current sense amplifier (LEMB-CSA), which is featured with continuously margin enhancement, offset suppression, small area, low peak current, and low energy consumption. We also propose the high area efficient, low power consumption near-memory-computing circuit which is embedded in sense amplifier to solve the design challenges we have mentioned before.
In TSMC 22 nm technology analysis, our proposed sense amplifier achieves 35.2% yield improvement and >80% lower tolerance on TMR-ratio than conventional sensing scheme. Moreover, the reduced number of IREF and pipeline current sampling method allows LEMB-CSA has 36.4% reduction in energy consumption, 40% reduction in peak current, and can tolerate 1.3 times offset current compared with MB-CSA published in ISSCC 2020. The speed overhead is only 18.2% compared with conventional read schemes (parallel sensing). The proposed near memory computing circuit can reduce 33.3% area overhead and 48.8% power consumption, and it can finish the shift/rotate logic computing in 1-cycle combined with read operation of the current sense amplifier.
Finally, our proposed scheme are verified in TSMC 22nm and 28nm CMOS process, the measurement results are depending on the 28nm test-mode memory macro. The access time of sense amplifier 8b sensing = 3.12ns at VDD = 0.9V, and the access time of 8b readout + 1b shift/rotate NMC operation mode required 3.29ns and consumed only 170ps over a typical memory access.

Contents
摘要 ii
Abstract v
致謝 viii
Contents ix
List of Figures xi
List of Tables xv
Chapter 1 Introduction 1
1.1 The Role of Memory in SoC products 1
1.2 Memory Landscape 2
1.3 Challenges of Flash Memory 5
1.4 Emerging Non-Volatile Memories 8
1.5 Von Neumann Bottleneck 13
1.6 Computing-In-Memory (CIM) 14
Chapter 2 Characteristic of STT-MRAM 16
2.1 Introduction of MRAM 16
2.2 Read and Write Operations of STT-MRAM 19
2.3 Recent Development of STT-MRAM 22
Chapter 3 Design Challenges of STT-MRAM 26
3.1 Sense Amplifier Design Challenges 26
3.1.1 Threshold Voltage in Process 26
3.1.2 Issues of STT-MRAM 28
3.2 Structures and Operations of Conventional Sensing Schemes 29
3.3 Previous Small Offset Current Sense Amplifiers 32
3.4 Previous art of Near-Memory-Computing (NMC) 38
3.5 Application of High Bandwidth Combined with NMC 39
Chapter 4 Proposed Circuits and Analysis 41
4.1 Motivation and Concept of Proposed Read Scheme 41
4.1.1 Two-stage Precharge and Sequential Sensing 43
4.1.2 Structure of Proposed LEMB-CSA 44
4.1.3 Operations of Proposed Sense Amplifier 45
4.2 Motivation and Concept of Proposed Near-Memory-Computing Scheme 56
4.2.1 Structure and operation of Proposed Near-Memory-Computing Unit (NMCU) 57
4.3 Analyses and Comparison 59
4.3.1 Tolerance of Low TMR-Ratio and Sensing Yield 60
4.3.2 CSA Performance Comparison 62
4.3.3 Precharged Array Speed Analyses 64
4.3.4 Comparison Table of Recent CSAs 66
4.3.5 NMC Performance Comparison 67
Chapter 5 Measurement Result and Conclusion 68
5.1 STT-MRAM Macro Implementation 68
5.2 Design for Test 70
5.3 Measurement results 71
5.4 Conclusions and Future Work 79
Reference 81

List of Figures
Figure 1 1 Tree Diagram of Memory Categories 3
Figure 1 2 Memory Hierarchy [12] 5
Figure 1 3 Challenges in Flash Memory Scaling [14] 6
Figure 1 4 Capacitive Coupling between Floating Gate Cell [15] 7
Figure 1 5 Number of Electrons on FG in Different Technology [16] 7
Figure 1 6 Structure of HfOX based 1T1R cell 9
Figure 1 7 Von Neumann architecture 14
Figure 1 8 (a) In-Memory-Computing architecture (IMC) (b) Near-Memory-Computing architecture (NMC) 15
Figure 2 1 MTJ structure and resistance states– Parallel state (P) and Anti-Parallel state (AP) 17
Figure 2 2 Cell architecture of (a) Magnetic-field switched, and (b) STT-MRAM [37] 18
Figure 2 3 STT-MRAM array architecture and R-I curve (R-I house) 19
Figure 2 4 (a) Write threshold current vs. Write pulse width (b) Switching Probability vs. Write current 20
Figure 2 5 (a) Die photo and Summary table of 4Gbit STT-MRAM chip [40] (b) The SEM image of 4Gbit-MTJ array [41] 22
Figure 2 6 (a) Die photo and Summary table of 4Mb STT-MRAM chip [42] and (b) Normalized LLC energy of SRAM and STT-MRAM [39] 23
Figure 2 7 (a) Enhanced read current window and (b) Die photo and Summary table of 16Mb perpendicular STT-MRAM chip [43] 24
Figure 2 8 Shmoo plot of read operation and (b) Summary table and Die photo of 32Mb N22 STT-MRAM chip [44] 24
Figure 3 1 (a) Distribution of 1T1MTJ (P and AP) resistance (b) LRS vs. R-ratio 29
Figure 3 2 (a) Structure and (b) waveform of Current-Mirror CSA (CM-CSA) 30
Figure 3 3 (a) Structure and (b) waveform of Current-Latch CSA (CL-CSA) 31
Figure 3 4 Current-Sampling-Based Sense Amplifier (CSB-SA) [55] 32
Figure 3 5 Time-Differential Current Sense Amplifier (TD-CSA) [56] 33
Figure 3 6 Covalent-Bonded Sense Amplifier (CB-CSA) [57] 34
Figure 3 7 Margin-Double Sense Amplifier (MD-SA) [58] 35
Figure 3 8 Structure of proposed Multibit Current Sense Amplifier (MB-CSA) [59] 36
Figure 3 9 (a) NC-FinFET-based 1-bit full-adder (b) Truth table of full adder [60] 38
Figure 3 10 (a) 10T bitcells and NMC circuit combine with SA. (b) Shifter/Rotator based on barrel shifter structure. [61] 39
Figure 3 11 Proposed work in STT-MRAM Macro compared with the conventional memory-logic-separated scheme 40
Figure 4 1 Macro Energy consumption for different IO numbers 42
Figure 4 2 (a) Conv. Parallel (b) Conv. Sequential (c) Proposed sensing method 42
Figure 4 3 (a) Current path (b) Peak Current of CL-CSA 43
Figure 4 4 (a) Conventional no precharged array (b) Precharged array 44
Figure 4 5 Structure of proposed Multibit Small Energy Current Sense Amplifier (LEMB-CSA) 45
Figure 4 6 (a) 1st 2b-output, SP1, quad current sampling 47
Figure 4 6 (b) 1st 2b-output, SP2, quad current subtraction and margin enhanced feedback 48
Figure 4 6 (c) 1st 2b-output, SP3, reusing latch and output (BL[3], BL[4]) 49
Figure 4 7 (a) 2nd 2b-output, SP1, quad current sampling 49
Figure 4 7 (b) 2nd 2b-output, SP2, quad current subtraction and margin enhanced feedback 50
Figure 4 7 (c) 2nd 2b-output, SP3, reusing and latch (BL[2], BL[5]) 50
Figure 4 8 (a) 3rd 2b-output, SP1, quad current sampling 51
Figure 4 8 (b) 3rd 2b-output, SP2, quad current subtraction and margin enhanced feedback 51
Figure 4 8 (c) 3rd 2b-output, SP3, reusing and latch (BL[1], BL[6]) 52
Figure 4 9 (a) 4th 2b-output, SP1, quad current sampling 52
Figure 4 9 (b) 4th 2b-output, SP2, quad current subtraction and margin enhanced feedback 53
Figure 4 9 (c) 4th 2b-output, SP3, reusing and latch (BL[0], BL[7]) 53
Figure 4 10 Structure of the Multibit Output Switches (MBOSWs) with 8 Output Latches 54
Figure 4 11 Operation formulas of each sub-phase 54
Figure 4 12 The sensing flow chart and detail in SP2 55
Figure 4 13 Waveform of proposed LEMB-CSA 55
Figure 4 14 Shift register consists of D flip-flop chain. 56
Figure 4 15 Memory macro architecture and structure of the proposed NMCU 57
Figure 4 16 NMC unit (NMCU) 1b-shift operation waveform and concept description 58
Figure 4 17 NMC unit (NMCU) 1b-rotate operation waveform and concept description 59
Figure 4 18 P-type MOSCAP Capacitance vs. Voltage Difference 60
Figure 4 19 Sampled Current Deviation Rate vs. Capacitance 61
Figure 4 20 Comparison of Sensing Yield vs. TMR-ratio 62
Figure 4 21 (a) MB-CSA performance comparison to CL-CSA parallel sensing [59] (b) LEMB-CSA performance comparison to MB-CSA 63
Figure 4 22 Performance of Sensing Different bits 64
Figure 4 23 Precharge vs. Conventional Access Time with different BL-Length 65
Figure 4 24 NMCU power, area comparison with conventional memory-logic-separated scheme 67
Figure 5 1 (a) Block diagram of 22nm macro architecture (b) Block diagram of 28nm macro architecture 69
Figure 5 2 (a) PAD delay TAC measurement (b) D Flip-Flop TAC measurement 71
Figure 5 3 Die Photo of the 28nm test-mode Macro 71
Figure 5 4 Measured Waveform of proposed LEMB-CSA TAC=3.12ns 73
Figure 5 5 Measured Waveform of CL-CSA with TAC=2.25ns 74
Figure 5 6 Measured Waveform of LEMB-CSA + 1 bit shift/rotate operation TAC-NMC=3.29ns 76
Figure 5 7 Measured Waveform of proposed SA + 4 bit shift operation 76
Figure 5 8 Measured Waveform of proposed SA + 4 bit rotate operation 77
Figure 5 9 Measured Access time Shmoo Plot of proposed works and CL-CSA 78

List of Tables
Table 1 1 Summary of Modern Flash Memory 8
Table 1 2 Comparisons of Emerging NVMs 12
Table 1 3 Summary of Recent Published Emerging NVMs 13
Table 2 1 Bias Condition of STT-MRAM Cell 21
Table 2 2 Summary table of Published STT-MRAM cells 25
Table 4 1 Comparison table of recent CSAs 66
Table 5 1 Summary Table of 28nm test-mode Memory Macro 80

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