本論文使用TSMC 65-nm CMOS標準製程實現一個三階四位元連續時間三角積分調變器，由於先進製程的進步以及對於高頻寬、高解析度的要求，連續時間三角積分調變器的架構因此被採用，除此之外連續時間三角調變器具有隱性抗交疊濾波器(Anti-Aliasing Filter,AAF)的特性，在系統上可以減緩前級AAF的要求。 連續時間三角調變器包含了一個由電阻電容式積分器所組成的三階迴路濾波器、四位元電流切換式數位類比轉換器以及操作於640MHz的四位元快閃式類比數位轉換器。我們使用取樣週期的一半來做額外回授路徑時間延遲的補償，同時設計一個負回授路徑避免額外回授路徑時間延遲造成系統穩定度下降。

整個連續時間三角積分調變器在32倍超取樣率下可以達到10-MHz的輸入頻寬，同時擁有87dB的動態範圍與93dB的訊號雜訊諧波比或14bit的有效位元數，在1.2V電源供應下，整體電路功率消耗為22.26mW，效能指標為612.2pJ/conv.

This paper introduce a third-order 4-bit continuous-time delta sigma modulator(CT ΣΔ Modulator) implemented in TSMC 0.65nm CMOS technology. Thanks to the advance CMOS processes and the requirement of high bandwidth and high resolution, the continuous-time delta sigma ADC has been growing recently. In addition, the CTDSM also has the important property of implicit anti-aliasing filter(AAF), and it can relax the spec of the AAF front. The proposed CTDSM consist of a third-order filter which is made up by R-C integrator、a 4-bit current-steering DAC and a 4-bit flash ADC operating at 640MHz clock frequency. This structure compensates the comparator time delay by taking a half-cycle excess loop delay. At the same time, we design a negative feedback loop to avoid the system instability caused by excess loop delay.

The whole CT ΣΔ Modulator achieve above 87 dB SNDR(14 ENOB) and 93dB SFDR over 10Mhz signal band. The power dissipation is 22.26 mW under 1.2V supply voltage, and the FOM is 612.2pJ/conv . The proposed circuity can be utilized in modern wireless communication.

Abstract I
Contents III
List of Tables VI
List of Figures VII
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 Introduction of Delta-Sigma Modulator 5
2.1 Analog to Digital Converter Classification 5
2.2 Nyquist Rate Sampling Theorem 7
2.3 Quantizer and Quantization Noise 8
2.4 Performance Metrics 11
2.5 Oversampling 15
2.6 ΔΣ modulator 17
2.6.1 Basic structure 17
2.6.2 First order ΣΔ modulator 19
2.6.3 Second order ΣΔ modulator 22
2.6.4 L-th order ΣΔ modulator 23
2.6.5 Stability 25
2.7 ΔΣ modulator main architectures 27
2.7.1 Single-bit and multi-bit quantizer 27
2.7.2 Cascade-of-integrators, feedback form(CIFB) 28
2.7.3 Cascade-of-integrators, feedforward form(CIFF) 29
2.7.4 Local feedback loops 30
2.7.5 Multi-stage, cascaded ΣΔ modulator 32
Chapter 3 System Level Design 34
3.1 CT ΣΔ Modulator Topology 34
3.2 Architecture of the Loop Filter 43
3.3 Loop Filter Coefficients 45
3.4 Excess loop delay 47
3.5 System Level Simulation 50
3.6 Circuit Nonideality 52
3.6.1 Non-idealities of CT Integrator 52
3.6.1.1 Finite Gain Bandwidth and Slew Rate 52
3.6.1.2 RC Time Constant Variation 56
3.6.2 Clock Jitter Influence 57
Chapter 4 Circuit Design and Implementation 60
4.1 Active-RC Integrator 60
4.1.1 Consideration of Resistor and Capacitor 60
4.1.2 Two-stage Opamp 62
4.2 Current-steering DAC 67
4.3 Quantizer 72
4.4 Transistor Level Simulation 74
4.5 Layout Consideration and Post-layout Simulation 76
Chapter 5 Conclusion and Future Work 79
5.1 Conclusion 79
5.2 Future Work 79
Reference 81

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