隨著人工智慧的浪潮愈演愈烈，深度學習演算法也愈趨成熟，因此神經
網路(NN) 硬體加速器的研究也如雨後春筍般出現，而記憶體內運算便是其
中一種打破傳統逢紐曼架構的記憶體導向特殊硬體。記憶體內運算的優勢
是同時具有運算以及儲存的功能，在記憶體端先進行運算再傳出結果，減
少移動的資料量，節省所需時間與能源。本篇論文針對一篇已經發表過的
非揮發記憶體內運算(nv-CIM) 作為實驗平台，其電路有著一個可以增進讀
取良率的電路(in-situ HRS-C)，而本篇論文利用了其電路的附帶特性，設計
一種特殊的神經網路權重量化流程，這個流程可以被有效加入到網路中，
使得在使用這個硬體進行AI 辨識時，在付出些微的精準度下降後，能使
TOPS/W 得到4.6 到10.51 的提升，同時也在網路訓練的過程中加入了CIM
的行為模型，這個行為模型能模擬感測放大器的行為，使訓練出來的網路
能包容因為CIM 中的類比運算誤差。進一步達到與純軟體接近的準確度。

With the rapid development of artificial intelligence and a more mature deep
learning algorithm, as a result, the number of DNN accelerator research has sprung
up, and In-Memory Computing is one of them, which is used to overcome the Von
Neumann bottleneck. The advantage of in-memory computing is that it has both
computation and storage functions. It performs operations on the memory side and
then transmits the results, reducing the amount of data moved, saving time and
energy. This paper aims at a published non-volatile memory in-memory computing
(nvCIM) as an experimental platform. It has a unique circuit (in-situ HRS-C)
that can improve the read yield. However, this thesis applies to this circuit’s additional
characteristics and provides a neural network parameter training process.
This training flow can be effectively added to the neural network. When this hardware
is used for AI classification, the proposed training flow makes it possible to
achieve a reasonable tradeoff between energy efficiency and inference accuracy.
It can improve TOPS/W from 4.6 to 10.51 with a negligible inference accuracy
drop. At the same time, the CIM behavior model also applies to the network training
process. This behavior model can simulate the sensing amplifier’s behavior.
The trained network can accommodate the CIM’s analog error and further achieve
accuracy close to pure software.

摘要 i
Abstract ii
致謝 iii
1 Introduction 1
1.1 The Development of Artificial Intelligence 1
1.1.1 Artificial Intelligent(AI) 2
1.1.2 Machine Learning(ML) 2
1.1.3 Deep Learning(DL) 3
1.2 Train a Neural Network 6
1.3 A Specialized Hardware - Artificial Intelligence Accelerator 7
1.4 Another Approach to AI Accelerator - Computing In Memory 8
2 Back Ground 10
2.1 Introduction for Emerging NVM Devices 10
2.2 Introduction for ReRAM CIM 12
2.2.1 Structure of ReRAM CIM 12
2.2.2 CIM Operation of ReRAM CIM 13
2.2.3 ReRAM CIM Mapping for AI Application 15
2.3 NN Model Building For ReRAM CIM 17
3 Previous Work 19
3.1 Previous ReRAM CIM Work 19
3.1.1 ReRAM CIM Structure-1 19
3.1.2 ReRAM CIM Structure-2 21
3.2 Previous Hardware Friendly Algorithm 23
3.2.1 Deep Compression 23
3.2.2 DoReFa Quantization Method 26
4 Proposed Algorithm and Analysis 29
4.1 Motivation of Proposed Algorithm 29
4.2 Concept of Proposed Algorithm 29
4.3 Details of Proposed Algorithm 31
4.3.1 Forward Propagation in HRS-FQ 33
4.3.2 Backward Propagation in HRS-FQ 35
4.4 Analysis and Comparison of the Proposed Algorithm 35
5 Conclusion and Future Work 38
References 39

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