隨著科技半導體產業日益進步，資料傳輸速度越來越快速且資料量越來越龐大，則高性能之鎖相迴路及時脈與資料回復電路……等電路架構扮演之角色也日益重要，又系統時脈速度大幅提升而產生之時脈與資料傳輸誤差問題越顯重要。在此產業背景下，為解決此問題，高速率、低抖動之時脈與資料回復電路成為熱門研究議題。
本論文研究主要是實現一個應用於USB 3.1之時脈與資料回復電路，為符合高速率之規格需求，本研究運用電壓電流轉換器(V-I Converter)取代電荷幫浦(Charge Pump, CP)，其速度影響主要來自於電流之充放電速率，因此我們應用電壓電流轉換器能有效減少電晶體(MOS)數量加快操作速率，但缺點是須在電流不匹配誤差(Current Mismatch)與充放電速率間取捨，然而幸運的是，電流不匹配誤差對時脈與資料回復電路之鎖定影響較小。並且為了縮小晶片面積，壓控振盪器(Voltage-Controlled Oscillator, VCO)我們在面積與相位雜訊(Phase Noise)間作取捨，由於本論文希望面積較小，因此使用環形振盪器(Ring Oscillator)做為晶片架構。由此設計我們不但可以操作在較高速率，亦能縮小晶片面積，達到高速率、低面積之時脈與資料回復電路。
本論文使用 TSMC 65nm 1P9M CMOS 製程 且供應電壓為1.2 V的環境下實現一個10Gbps全速率時脈與資料回復電路。輸入資料為10 Gbps PRBS7 ，還原時脈速率為10 GHz，功率消耗為30.1 mW，電路面積為72.5 μm x 47.5 μm 。

With the advancement of technology, the speed of data transmission is getting faster and the amount of data is getting bigger. The role of high-performance phase-locked loop and clock and data recovery circuit architecture is also increasingly important. The problem of clock and data transmission errors caused by the greatly increased system clock speed becomes more important.Under this industry background, to solve this problem, high-speed and low-jitter clock and data recovery circuits have become popular research topics.
The research in this paper is mainly to implement a clock and data recovery circuit applied to USB 3.1. In order to meet the requirements of high-speed specifications, this study uses a voltage - to - current converter to replace the charge pump. The speed effect mainly comes from the current charge-discharge rate, so we use a voltage-to-current converter can effectively reduce the number of transistors and speed up the operation rate, but the disadvantage is that there is a trade-off between the current mismatch and the charge-discharge rate. Fortunately, the current mismatch has little effect on the locking of clock and data recovery circuit. In order to reduce the chip area, the voltage controlled oscillator is a trade-off between the area phase noise. Due to the primary consideration of area in this paper, we use a ring oscillator to complete the chip architecture. From this design, we can not only operate at a higher rate, but also reduce the chip area to achieve a high-speed, low-area clock and data recovery circuit.
The chip is fabricated by a 65 nm 1P9M CMOS process with a supply voltage of 1.2 V, and a 10 Gbps full rate clock and data recovery circuit is realized. The input data is 10 Gbps PRBS7 pattern, the restoration clock rate is 10 GHz, the power consumption is 30.1 mW, and the circuit area is 72.5 μm x 47.5 μm.

摘要i
Abstract(英文摘要)ii
目錄iii
圖目錄vi
表目錄x
第一章 序論1
1.1 研究動機1
1.2 論文簡介4
第二章 高速串列傳輸訊號5
2.1 簡介5
2.2 資料傳輸型態5
2.2.1 隨機二進位訊號編碼種類6
2.2.2 隨機二進位訊號編碼特性6
2.2.3 資料編碼機制8
2.3 時脈抖動介紹9
2.3.1 隨機性時脈抖動10
2.3.2 固定性時脈抖動11
2.3.3 時脈抖動量測15
2.4 眼圖量測及分析21
2.5 位元錯誤率22
第三章 時脈與資料回復電路簡介25
3.1 前言25
3.2 時脈與資料回復電路簡介26
3.2.1 相位偵測器26
3.2.2 電壓-電流轉換器28
3.2.3 壓控振盪器29
3.3 時脈與資料回復電路型態33
3.3.1 鎖相迴路式時脈與資料回復電路[18]-[19]33
3.3.2 混合鎖相迴路/延遲鎖相迴路式時脈與資料回復電路[21]-[22]35
3.3.3 相位選擇式時脈與資料回復電路[23]36
3.3.4 雙路徑式時脈與資料回復電路[24]37
3.3.5 數位時脈與資料回復電路[25]38
3.4 性能指標介紹與討論40
3.4.1 取樣速率41
3.4.2 抖動轉移函數42
3.4.3 抖動容忍度43
第四章 10 Gbps 時脈與資料回復電路架構設計與實現45
4.1 電路架構45
4.2 系統分析47
4.2.1 線性模型系統分析47
4.2.2 頻寬對系統之影響55
4.3 行為模擬59
4.3.1 線性系統60
4.3.2 系統迴路62
4.4 相位偵測器64
4.4.1 線性相位偵測器64
4.4.2 非線性相位偵測器67
4.4.3 結果分析與比較71
4.5 電壓-電流轉換器72
4.6 電壓控制振盪器74
第五章 模擬結果與電路佈局79
5.1 迴路模擬結果79
5.1.1 佈局前模擬79
5.1.2 時脈抖動80
5.2 電路佈局81
5.2.1 晶片佈局81
5.2.2 佈局後模擬81
5.3 佈局前後分析與比較83
第六章 結論85
6.1 總結85
6.2 未來展望86
參考文獻87

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