帳號:guest(216.73.216.146)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):陳柏霖
作者(外文):Chen, Po-Lin
論文名稱(中文):具備數位通訊介面之雙星型串接式轉換器測試平台開發
論文名稱(外文):Development of the Double-Star-Connected Cascaded Converter Testbed with Digital Communication Interface
指導教授(中文):鄭博泰
指導教授(外文):Cheng, Po-Tai
口試委員(中文):金藝璘
唐丞譽
口試委員(外文):Kim, Katherine A.
Tang, Cheng-Yu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:107061502
出版年(民國):109
畢業學年度:108
語文別:中文
論文頁數:64
中文關鍵詞:模組化多階層串接式轉換器場效可規劃邏輯閘陣列序列埠串列傳輸七階雙星型串接式轉換器測試平台相位移脈波寬度調變直流鏈電壓控制策略
外文關鍵詞:Modular multilevel cascaded converterField programmable gate arrayTx/Rx serial port transmissionSeven-level double-star-connected cascaded converter testbedPhase-shifted pulse width modulationDC bus voltage control strategy
相關次數:
  • 推薦推薦:0
  • 點閱點閱:149
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
近年來,隨著人們對電力的需求日益增長,為發電與輸電系統迎來了新的挑戰,加上環境保護意識的興起,各國政府開始致力於再生能源的發展。由於模組化多階層串接式轉換器(Modular Multilevel Cascaded Converters, MMCCs)可分散開關應力且具有高擴張性,因此很適合用在太陽能光伏系統、風力發電機組等中壓層級之功率轉換上。然而因為串接式轉換器是藉由模組與模組之間的相互連接而形成,若欲提升串接模組的個數,不僅會增加通訊網路與模組間數位訊號的數量,系統線路連接的複雜度與成本也會相對提高,故無法輕易地增加串接模組的個數。

本論文將以場效可規劃邏輯閘陣列(FPGA)為通訊核心,並且結合感測板、保護板及模組板等硬體電路,設計規劃出一台具備數位通訊介面之七階雙星型串接式轉換器(Double-Star-Connected Cascaded Converter, DSCC)測試平台。為了降低系統線路之複雜度,測試平台採用序列埠(Tx/Rx)串列傳輸之通訊方式,利用兩條線進行雙向資料的交換,同時也能減少數位處理器所需負擔的訊號數量。

最後於雙星型串接式轉換器測試平台上進行開迴路與閉迴路實驗。在開迴路實驗中,利用相位移脈波寬度調變可以實現多階層的輸出電壓;而在閉迴路的實驗裡,則可透過實驗結果驗證直流鏈電壓控制策略之正確性。
In recent years, with the growing demand for electricity and the raising awareness on environmental protection, governments start working on the development of renewable energy. Due to less switch device stress and high expansion, the modular multilevel cascaded converters (MMCCs) are suitable for medium-voltage power conversion applications, such as photovoltaics (PV) system and wind turbine. However, the MMCCs are composed of the interconnection between modules. If the number of the serial modules increases, it not only increases the digital signals between communication network and the modules, but also raises the complexity of system connection and the cost.

To build a seven-level double-star-connected cascaded converter (DSCC) testbed with digital communication interface, FPGAs and PCB circuit boards are used in the testbed construction. In addition, Tx/Rx serial port transmission is applied on the testbed in order to reduce the complexity of system connection. Serial port transmission not only reduces the signals connected to the digital processors, but also needs only two wires for two-way data exchanging and communicating.

Finally, the open-loop and the closed-loop tests of DSCC are operated on the testbed. In the open-loop test, multilevel output voltage can be achieved by phase-shifted pulse width modulation;and in the closed-loop test, the accuracy of DC bus voltage control strategy can be verified through the experimental results.
摘要----------------------------------------------------------------I
致謝--------------------------------------------------------------III
目錄---------------------------------------------------------------IV
圖目錄------------------------------------------------------------VII
表目錄--------------------------------------------------------------X
第一章、 緒論-------------------------------------------------------1
1.1 研究背景與動機--------------------------------------------------1
1.2 論文內容大綱----------------------------------------------------3
第二章、 文獻回顧---------------------------------------------------4
2.1 簡介------------------------------------------------------------4
2.2 相位移脈波寬度調變技術-------------------------------------------4
2.3 七階雙星型串接式轉換器-------------------------------------------6
2.3.1 電路架構及參數說明---------------------------------------------6
2.3.2 平均電壓控制策略----------------------------------------------8
2.3.3 平衡電壓控制策略---------------------------------------------10
第三章、 測試平台之系統架構介紹-------------------------------------11
3.1 簡介-----------------------------------------------------------11
3.2 系統架構概述---------------------------------------------------11
3.3 數位通訊介面之建置----------------------------------------------14
3.3.1 數位通訊介面之架構介紹----------------------------------------14
3.3.2 中央FPGA(命令端)功能配置--------------------------------------16
3.3.3 中央FPGA(感測端)功能配置--------------------------------------18
3.3.4 模組FPGA(命令端)功能配置--------------------------------------19
3.3.5 模組FPGA(感測端)功能配置--------------------------------------21
3.4 感測板電路介紹-------------------------------------------------23
3.4.1 感測板功能說明-----------------------------------------------23
3.4.2 三相交流電壓感測電路------------------------------------------25
3.4.3 三相交流電流感測電路------------------------------------------26
3.5 保護板電路介紹-------------------------------------------------27
3.5.1 保護板功能說明-----------------------------------------------27
3.5.2 參考電壓電路-------------------------------------------------30
3.5.3 直流側保護訊號集結電路----------------------------------------31
3.5.4 三相交流過電流保護電路----------------------------------------32
3.5.5 整體保護訊號集結電路------------------------------------------33
3.5.6 柔充機制啟動電路---------------------------------------------34
3.5.7 開關訊號控制電路---------------------------------------------35
3.6 模組板電路介紹-------------------------------------------------36
3.6.1 模組板功能說明-----------------------------------------------36
3.6.2 參考電壓電路-------------------------------------------------38
3.6.3 直流鏈電壓感測電路--------------------------------------------39
3.6.4 直流側過電壓保護電路------------------------------------------41
3.6.5 直流側過電流保護電路------------------------------------------42
3.6.6 開關訊號輸出電路---------------------------------------------43
3.6.7 返馳式轉換器模組---------------------------------------------44
3.6.8 閘極驅動電路-------------------------------------------------45
3.6.9 全橋轉換器電路-----------------------------------------------46
第四章、 測試平台之實驗結果-----------------------------------------47
4.1 簡介-----------------------------------------------------------47
4.2 單相系統之開迴路實驗--------------------------------------------51
4.3 三相系統之閉迴路實驗--------------------------------------------55
第五章、 結論與未來展望---------------------------------------------61
5.1 結論-----------------------------------------------------------61
5.2 未來展望-------------------------------------------------------62
參考文獻-----------------------------------------------------------63
1. H. Akagi, "Classification, Terminology, and Application of the Modular Multilevel Cascade Converter (MMCC)," in IEEE Transactions on Power Electronics, vol. 26, no. 11, pp. 3119-3130, Nov. 2011.

2. I. R. F. M. P. da Silva, C. B. Jacobina, A. C. Oliveira, G. A. de Almeida Carlos and M. B. d. R. Corrîa, "Hybrid multilevel inverter system for Open-End Winding (OEW) induction motor drive based on Double-Star Chopper-Cells (DSCC) converter," 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), Charlotte, NC, 2015, pp. 2380-2386.

3. M. Hagiwara, I. Hasegawa and H. Akagi, "Start-Up and Low-Speed Operation of an Electric Motor Driven by a Modular Multilevel Cascade Inverter," in IEEE Transactions on Industry Applications, vol. 49, no. 4, pp. 1556-1565, July-Aug. 2013.

4. Xu She and A. Huang, "Circulating current control of double-star chopper-cell modular multilevel converter for HVDC system," IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society, Montreal, QC, 2012, pp. 1234-1239.

5. K. Oguma, F. Sasongko, M. Hagiwara and H. Akagi, "Low-voltage ride-through capability of an HVDC transmission system using two modular multilevel cascade converters (MMCC-DSCC)," 2015 IEEE International Future Energy Electronics Conference (IFEEC), Taipei, 2015, pp. 1-6.

6. W. Liu, R. Jayakar, W. Song and A. Q. Huang, "A modular digital controller architecture for multi-node high power converter applications," 31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON 2005., Raleigh, NC, 2005, pp. 6 pp.-.

7. Poh Chiang Loh, D. G. Holmes and T. A. Lipo, "Implementation and control of distributed PWM cascaded multilevel inverters with minimal harmonic distortion and common-mode voltage," in IEEE Transactions on Power Electronics, vol. 20, no. 1, pp. 90-99, Jan. 2005.

8. B. Li, R. Yang, D. Xu, G. Wang, W. Wang and D. Xu, "Analysis of the Phase-Shifted Carrier Modulation for Modular Multilevel Converters," in IEEE Transactions on Power Electronics, vol. 30, no. 1, pp. 297-310, Jan. 2015.

9. M. Hagiwara and H. Akagi, "Control and Experiment of Pulse Width Modulated Modular Multilevel Converters," in IEEE Transactions on Power Electronics, vol. 24, no. 7, pp. 1737-1746, July 2009.

10. S. Yang, Y. Tang and P. Wang, "Distributed Control for a Modular Multilevel Converter," in IEEE Transactions on Power Electronics, vol. 33, no. 7, pp. 5578-5591, July 2018.

11. S. Yang, S. Liu, J. Huang, H. Su and H. Wang, "Control Conflict Suppressing and Stability Improving for an MMC Distributed Control System," in IEEE Transactions on Power Electronics, May. 2020.

12. M. Hagiwara, R. Maeda and H. Akagi, "Control and Analysis of the Modular Multilevel Cascade Converter Based on Double-Star Chopper-Cells (MMCC-DSCC)," in IEEE Transactions on Power Electronics, vol. 26, no. 6, pp. 1649-1658, June 2011.

13. S. Du and J. Liu, "A Study on DC Voltage Control for Chopper-Cell-Based Modular Multilevel Converters in D-STATCOM Application," in IEEE Transactions on Power Delivery, vol. 28, no. 4, pp. 2030-2038, Oct. 2013.

14. I. R. F. M. P. da Silva, C. Brandão Jacobina and A. C. Oliveira, "Single-Phase AC–AC Double-Star Chopper Cells (DSCC) Converter Without Common DC-Link Capacitor," in IEEE Transactions on Industry Applications, vol. 51, no. 6, pp. 4642-4652, Nov.-Dec. 2015.

15. Y. Okazaki, H. Matsui, M. M. Muhoro, M. Hagiwara and H. Akagi, "Enhancement on capacitor-voltage-balancing capability of a modular multilevel cascade inverter for medium-voltage synchronous-motor drives," 2015 IEEE Energy Conversion Congress and Exposition (ECCE), Montreal, QC, 2015, pp. 6352-6359.
(此全文未開放授權)
電子全文
中英文摘要
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *