半導體測試產業在近年來，經營環境變化快速與相關產業競爭較量，使得客戶不論對品質、成本、交期與服務的要求已是愈來愈高，然而測試部品續航力就是非常關鍵的競爭力指標，若能提高並有效掌控測試部品續航力，則能獲得差異化的競爭優勢。

隨著科技的日新月異，產品規格越做越小，效能需求也越來越高，測試運作所發生定位精度件數也越來越多，直接影響到生產稼動率，更嚴重會造成部品損壞與IC材料壓壞。換言之，為維持測試效率，在分類機與部件壓塊定位精度就更顯得重要。

本研究利用六標準差設計驗證架構，並運用品質機能展開、失效模式分析、田口實驗及軟體模擬探討，進行產品開發，有效的縮短開發時間，以較低成本改善了「吸取IC材料所發生定位精度不佳」的技術瓶頸與障礙的排除，達到架構最佳部件壓塊定位之設計。

In recent years, the rapid change of business environment in the semiconductor test industry has been more competing than the related industries, which results in higher and higher customers' requirements in terms of service quality, cost, and delivery time. However, the endurance of test parts is a key competitiveness indicator. If companies can improve and effectively control the endurance of test parts, companies can gain a differentiated competitive advantage.

With the ever-changing development in science and technology, the product specifications are getting smaller and smaller, the efficiency demand is getting higher and higher, and the number of positioning accuracy pieces in the test operation is also increase, which directly affects the production rate, and even more seriously causes part damage and IC material crushing. In other words, in order to maintain the test efficiency, it is obviously more important to improve the positioning accuracy of the component block and the Handler classifier machine.

In this study, six sigma design framework is adopted to verify the jig and tooling structure, and quality function deployment, failure mode analysis, Taguchi experiment and software simulation are applied to develop new tooling block. The proposed method has effectively shortened the development time, improved the technical bottleneck and obstacled removal of "poor positioning accuracy of IC material absorption" at a lower cost, so as to achieve the design of the best component block positioning of the structure.

摘要.............................................................I
ABSTRACT........................................................II
誌謝............................................................III
目錄.............................................................IV
圖目錄...........................................................VI
表目錄..........................................................VII
第一章 緒論........................................................1
1-1 研究背景.......................................................1
1-2 研究動機.......................................................2
1-3 研究目的.......................................................3
1-4 論文架構.......................................................3
第二章 文獻回顧探討 ..................................................5
2-1六標準差設計(Design for Six Sigma, DFSS).........................5
2-2品質機能展開(Quality function Deployment, QFD)...................9
2-3失效模式與效應分析FMEA...........................................12
2-4田口方法(Taguchi Methods)......................................16
2-4-1直交表(Orthogonal Array)及信號雜音比(Signal to Noise Ratio)....20
第三章 研究方法....................................................22
3-1釐清...........................................................23
3-1-1品質機能展開..................................................24
3-2失效模式與效應分析FMEA...........................................26
3-2-1設計失效模式與效應分析實施方法與步驟..............................26
3-3最佳化設計......................................................30
3-3-1實驗流程......................................................30
3-3-2田口直交表....................................................31
3-3-3田口品質工程-產品/製程參數......................................33
3-3-4訊號與雜訊比(Signal to Noise Ratio, S/N)......................34
3-4驗證...........................................................37
3-4-1模擬分析(Simulation)..........................................37
第四章 個案分析.....................................................38
4-1個案公司背景.....................................................38
4-2半導體測試流程及架構..............................................40
4-2-1 分類機架構...................................................41
4-2-2測試配件治具..................................................42
4-3 現況問題描述...................................................43
4-3-1問題探討與分析.................................................44
4-4定義-目標需求...................................................45
4-4-1品質機能展開..................................................45
4-5設計失效模式與效應分析............................................46
4-6訊號與雜訊比分析及最佳參數組合.....................................49
4-7驗證-Verify....................................................52
4-8效益及設計標準化.................................................53
第五章結論與建議....................................................54
5-1結論...........................................................54
5-2研究限制........................................................54
5-3未來研究方向.....................................................54
參考文獻...........................................................56

圖目錄
圖1-1 定位不佳示意圖（本研究整理）......................................1
圖1-2 2019年IC產業產值（來源：台灣半導體產業協會、工研院產科國際所）.........2
圖1-3 研究流程圖.....................................................4
圖2-1 五標準差之牆(蘇朝墩，2009).......................................5
圖2-2 六標準差設計流程步驟(本研究整理)...................................7
圖2-3 先期產品品質規劃(博威公司官方網頁)................................14
圖3-1 IDOV研究流程及手法.............................................23
圖3-2 品質屋(House of Quality)......................................25
圖3-3 品質屋四階段(吳貴彬、陳相如，2004)...............................26
圖3-4 整合流程模式(本研究整理)........................................27
圖3-5 實驗流程步驟(本研究整理)........................................30
圖3-6 直交表符號....................................................32
圖3-7 直交表(蘇朝敦，2009)...........................................33
圖3-8 產品/製程之參數圖(蘇朝敦，2009)..................................34
圖4-1 IC Insights、工研院IEK、SIPO整理(2018/07)......................38
圖4-2 108年財報資訊(個案公司提供).....................................39
圖4-3 專利與文章發表件數統計(個案公司提供)..............................39
圖4-4 半導體測試流程(本研究整理)......................................41
圖4-5 分類機系統(Hontech官方網頁)....................................42
圖4-6 IC測試配件治具(本研究整理)......................................43
圖4-7 IC測試動作解析(本研究整理)......................................44
圖4-8 壓塊示意圖....................................................45
圖4-9 品質機能展開圖(本研究整理).......................................46
圖4-10 主效應分析圖..................................................51
圖4-11 訊號與雜訊比分析圖.............................................51
圖4-12 壓塊設計(本研究整理)...........................................52
圖4-13 壓塊模擬結果(本研究整理)........................................53

表目錄
表2-1 一般六標準差與DFSS的比較(蘇朝墩，2009).............................6
表3-1 失效模式與效應分析嚴重性衡量標準表(本研究整理).......................27
表3-2 失效模式與效應分析發生性衡量標準表(本研究整理).......................28
表3-3 失效模式與效應分析偵測性衡量標準表(本研究整理).......................28
表3-4 設計失效模式與效應分析表格範例.....................................29
表3-5 拉丁方格設計 ....................................................31
表4-1 設計失效模式與效應分析展開圖(本研究整理)............................47
表4-2 參數因子與水準對照表.............................................50
表4-3 最佳參數結果表..................................................50
表4-4 變異數分析表 ....................................................52
表4-5 效益改善前後比較(本研究整理)......................................53

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網路資源
1.個案公司網頁，(https://www.spil.com.tw/)
2.世界半導體貿易統計協會(WSTS)，(https://www.wsts.org/)
3.鴻勁精密股份有限公司，(https://www.hontech.com.tw/products_detail.php?M=0&Key=11)
4.半導體積體電路測試概論，白安鵬，(http://ictesting-tom.blogspot.com/2008/10/blog-post_02.html )
5.DOE實驗設計原理與應用，(https://kknews.cc/zh-tw/news/2brjvoy.html)
6.經濟部工業局智慧電子產業計畫推動辦公室，(https://www.sipo.org.tw/industry-overview/industry-ranking.html)
7.台灣半導體產業學會，(https://www.tsia.org.tw/PageContent?pageID=1)
8.EET電子工程專輯，(https://www.eettaiwan.com/)
9.Autodesk company，(https://www.autodesk.com/company)
10.中華民國品質學會，(http://www.csq.org.tw/mp.asp?mp=1)
11.社團法人中國工業工程學會，(https://www.ciie.org.tw/)
12.博威顧問服務股份有限公司，(http://www.broadway.com.tw/management.php?id=4)