未來電子元件之發展朝向高腳數、微小化與輕薄化的趨勢，而與之息息相關的電子封裝技術也隨之蓬勃發展，扇出型面板級封裝(Fan-Out Panel Level Packaging, FO-PLP)是在電子封裝產業中最新的趨勢之一，面板級封裝是指切割好的晶片會先在矩形載板上進行封裝製程，待製程完成後再進行切割成為單顆封裝。
相較於傳統12吋的晶圓級封裝，面板級封裝不僅在使用面積上大上數倍，且由於晶片和載板皆為矩形，不似晶圓級封裝在邊角的部分無法被利用，因此材料使用率較高。由於上述的原因，面板級封裝在材料使用率上及成本上都相較晶圓級封裝有優勢。
在封裝製程中，由於封膠製程中會將結構加熱至某一溫度後再降回室溫接續下一製程的製作，溫度的變化會造成結構發生翹曲與晶片位移，若翹曲量過大或晶片位移過大會導致下個製程無法被進行，因此對於兩者的掌控是非常重要的，在本研究，將只專注於翹曲變形之預估。
在封膠製程中，造成翹曲的主要原因有兩個，一是在溫度變化下，由於材料的熱膨脹係數不匹配造成不同材料間的收縮量不同而導致翹曲；二是由於封膠製程中，環氧模壓樹脂(Epoxy Molding Compound)在升溫時會發生固化反應而造成體積收縮使得翹曲的效應更加顯著。
由於翹曲量對於製程進行有著顯著的影響，因此需要預估翹曲量的發生以避免結構下的翹曲量過大，本研究用來預估翹曲量的方法為使用有限元素法(Finite Element Method, FEM)來模擬實驗，正確的模擬不僅能和實驗的結果相符合，也能在開發產品時省下大量的時間。由於封膠製程中所使用的環氧模膠樹脂為熱固性材料，其固化而導致體積收縮的反應非常複雜，因此在本研究中會使用等效熱膨脹係數法(Equivalent CTE)來簡化計算過程，並建立一可靠之扇出型面板級封裝模型。
當有限單元模型的模擬被認證後，會依照相同的建模流程來建立不同幾何尺寸結構下的扇出型面板之翹曲量資料庫，並利用機器學習之方法訓練電腦自行學習在面板級封裝中結構幾何對於翹曲量之影響，當機器成功學習到其中之關係後，只要向電腦中輸入關於面板級封裝中幾何結構之尺寸，電腦便可在幾秒之內得出一對應的翹曲量，並且此翹曲量是非常接近實驗值的答案。
而在本文中所使用之機器學習模型為修正型卷積神經網路，其架構與經典卷積神經網路相似，皆會使用卷積層、池化層以及全連接神經網路，但與經典卷積神經網路之主要差異在於卷積層之部分，在本研究中所使用之卷積層的用途為結構翹曲量之邊緣偵測，用來尋找對於訓練模型較有效之參數。
本研究旨在利用機器學習之方法建立一可靠之神經網路，使任何人在此扇出型面板級封裝製程下輸入面板結構參數即可得到相對應之翹曲量，且此翹曲量不因輸入者不同而有所差異，不僅可減少使用者所造成的誤差，也能減少在模擬上所耗費之時間。

In the future, the development of electronic components is trending toward higher I/O number, miniaturization, and thinning, and the electronic packaging technology closely related to it is also flourish. Fan-Out Panel Level Packaging (FO-PLP) is one of the latest trends in the electronic packaging industry. Panel-level packaging means that the chip is cut first and then packaged on a rectangular carrier. After the process is completed, it is cut into a single package. Compared with the conventional 12-inch Wafer-level packaging, Panel-level packaging is not only a multiple of the area of use, and because the Wafer-level package can not be used in the corners and the chip and carrier of Panel Level packaging are rectangular, so the material usage is higher. For the reasons above, Panel-level packaging has advantages over wafer-level packaging in terms of material usage and cost.
During the packaging process, since the structure is heated to a certain temperature in the process and then cooled down to the room temperature to continue the next process, the temperature change will cause warpage and die shift in the structure. If the warpage or die shift is too large, the next process is hard to be done, so it is very important to control both the warpage and die shift. But in this study, we will only focus on the prediction of warpage deformation.
In the molding process, there are two main reasons causing the warpage. First, under temperature change, the thermal expansion coefficient of the material does not match, resulting in different shrinkage between different materials and then causing warpage. Second, during the molding process, Epoxy Molding Compound undergoes a curing reaction at a temperature rise to cause volume shrinkage and make the effect of warpage significant.
Since the amount of warpage has a significant influence on the fabrication process, it is necessary to estimate the amount of warpage to avoid excessive warpage under the structure. The method used to estimate the warpage in this study is the finite element method (FEM). We use FEM to simulate the experiment. A good simulation can not only meet the experimental results, but also save a lot of time when developing the product. Because the epoxy molding compound used in the molding process is a thermosetting material, the reaction of solidification and volume shrinkage is very complicated, so in this study, the equivalent thermal expansion coefficient method is used to simplify the calculation process and establish a reliable Fan-Out Panel-Level Packaging model.
After the simulation of the finite element model is verified, the warpage database of the fan-out panel level packaging under different geometrical dimensions will be established according to the same modeling process, and the machine learning method is used to train the computer to learn the relationship between the panel-level package geometry and warpage. After the machine successfully learns the relationship, the computer can get a corresponding warpage in a few seconds by inputting the dimensions of the geometry of the panel-level package to the computer, and this amount of warpage is an answer very close to the experimental value.
The machine learning model used in this paper is a modified convolutional neural network. Its architecture is similar to that of classical convolutional neural networks. It uses convolution layer, pooling layer, and fully-connected neural networks. But with classic architecture, the main difference between the convolutional neural network is the part of the convolution layer. The purpose of the convolutional layer used in this study is to detect edge of the structural warpage, which is used to find the parameters that are more effective for the training model.
This study aims to establish a reliable neural network by means of machine learning. Anyone can input the structural parameters of the panel under this fan-out panel-level packaging process to obtain the corresponding amount of warpage, and the amount of warpage is stable and correct no matter who inputs the value. It can not only reduce the error caused by the user, but also reduce the time spent on the simulation.

摘要 I
Abstract III
目錄 V
圖目錄 IX
表目錄 XII
第一章 緒論 1
1.1 簡介 1
1.2 文獻回顧 2
1.3 扇入型覆晶與晶圓級封裝製程 12
1.4 扇出型晶圓級與面板級封裝製程 14
1.5 扇出型晶圓級與面板級封裝之晶片偏移現象 16
1.6 研究動機與目標 17
第二章 基礎理論 18
2.1 有限元素法理論 18
2.1.1 有限元素法之線彈性有限單元理論 18
2.2 有限元素法接觸理論 20
2.2.1 罰函數法 21
2.2.2 拉格朗日乘子法 22
2.2.3 增廣拉格朗日乘子法 22
2.3 翹曲現象 22
2.3.1 溫度變化導致翹曲現象 23
2.3.2 固化反應導致翹曲現象 23
2.4 P-V-T-C方程式 24
2.5 等效熱膨脹係數法 25
2.6 機器學習 Machine Learning 28
2.6.1 神經網路與感知器 29
2.6.2 人工神經網路 Artificial Neural Network 30
2.6.3 更新神經網路之梯度下降法 Gradient Descent 31
2.6.4 學習速率常數 Learning Rate 33
2.6.5 反向誤差傳播法 Backpropagation 36
2.6.6 激活函數 Activation Function 38
2.6.7 卷積神經網路 Convolutional Neural Network 40
2.6.8 圖像補零法 Zero Padding 43
2.6.9 增量學習 Incremental Learning 44
2.6.10 遷移學習 Transfer Learning 46
2.7 機器學習優化方法與結果評估 47
2.7.1 資料前處理 Preprocessing 47
2.7.2 交叉驗證 Cross Validation 49
2.7.3 神經網路之擬和度 Underfitting與Overfitting 50
2.7.4 正規化 Regularization 50
2.8 機器學習之平台 53
2.8.1 Scikit-Learn Package 53
2.8.2 Keras 54
第三章 有限單元模型建立 55
3.1 扇出型面板級封裝模型 55
3.1.1 材料參數與元素尺寸設定 56
3.1.2 邊界條件與負載求解設定 58
3.2 扇出型面板級封裝翹曲量分析 59
3.2.1 載板脫離製程翹曲量分析 61
第四章 機器學習之流程 64
4.1 機器學習資料庫 65
4.1.1 數據建立之方法 66
4.1.2 面板尺寸對於翹曲量之影響分析 69
4.2 訓練神經網路之資料點選取 75
4.2.1 閥值之數據處理 76
4.2.2 邊緣檢測 Edge Detection之數據處理 78
4.3 池化層 Pooling Layer 81
第五章 結果與討論 84
5.1 尋找最佳參數配置 84
5.2 使用108筆訓練資料之結果 93
5.2.1 使用Full Array訓練資料庫對於訓練模型之影響 93
5.2.2 正規化對於訓練模型之影響 97
5.2.3 使用Feature Map訓練資料庫對於訓練模型之影響 101
5.3.4 使用不同資料庫對於訓練模型影響之比較 105
5.3 Incremental Learning 110
5.3.1 使用27-27資料庫進行Incremental Learning 110
5.3.2 使用27-54資料庫進行Incremental Learning 113
第六章 結論與未來工作 119
第七章 參考文獻 121

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