肇因於半導體技術的迅速發展，前瞻晶片內之元件目前已隨著莫爾定律微縮至奈米尺度。其中，互補式金氧半導體(CMOS)結構長期皆為整體積體電路之主流技術。然而，在節點技術急遽微縮以迎合效能提升的需求下，亦面臨在製程與效能等方面之巨大挑戰。因此，發展出具有金屬閘極/高介電係數之介電層(Metal Gate/High-k Dielectric)、應變工程技術、具高載子遷移率之新式材料，以及下一世代之三維鰭式元件結構。在研發與設計階段，若需製造與量測元件效能，通常需要大量的技術與時間成本投入，故若能夠簡單快速並準確預估元件效能，為半導體元件研發與競爭力提升之重要關鍵之技術。
有鑑於此，本研究中建立力學解析模型，用於計算載子傳輸通道之應力分佈。藉由導入應變工程技術之元件，產生機械應變致使傳輸通道之材料能帶結構改變，進而提升半導體元件之電性表現。應變工程之主要應力源主要包含，金氧半場效電晶體(MOSFET)結構其源/汲極(Source/Drain)晶格不匹配應力和淺溝槽隔離層(STI)內含殘留應力。利用此研究推導之解析模型估算上述諸項應力源對於元件通道所產生之應力分佈與力學響應，並以目前主流技術之結構尺寸與材料種類為參數予以探討。此外，藉有限元素模擬分析，驗證該解析模型的準確性。此解析解以半導體元件為推導架構，分別以一維通道方向，以及二維通道與厚度方向之力學理論為核心，推導MOSFET結構在應力源作用下之力學響應。
另一方面，本研究亦針對數個先進半導體元件，包含對於矽基、鍺基、三五族基等高載子遷移率之元件進行探討。藉由壓阻效應之應力-電阻率關係進一步量化通道之載子遷移率增益。同時，進一步地計算短通道CMOS之工作電流，以電性表現說明元件效能的實際增益。本研究所發展解析模型之應力與電性解析結果，能夠有效地幫助半導體元件進行更有效率的設計，期以做為半導體產業使用應變工程技術時之研究參考。

Due to the quickly development of semiconductor technology, the components whithin the innovative chip have been narrowed down to the nanometer scale in accordance with Mohr’s law. To meet the demand of operated enhancement, the mainstream of Metal-Oxide Semiconductor Field-Effect-Transistor (MOSFET) architectures at advanced nodal technology is to face huge challenges in terms of processes and performance. Consequently, both the high-k/metal gate structures combined with the use of strained engineering and novel materials having high carrier mobility are presented. In the stages of R&D and design, the consumption of technology capability and requirement of time cost investment are usually expected to manufacture and measure the electrical performances of concerned devices. Accordingly, it becomes the key of boosting up the R&D competitiveness of semiconductor devices if their related performances could be easily, quickly and accurately estimated.
For the above-mentioned reason, an analytical model based on mechanics is established in this study to calculate the stress distribution of the carrier transport channel. Through the mechanical strain induced by the strained components within MOSFET devices, the band structure of channel material is changed to promote their electrical performances. The foregoing stress resources considered in the proposed analytical model are composed of lattice-mismatch stress of source/drain (S/D) and intrinsic stressed shallow trench isolation (STI). The analytical model derived in this research is used to estimate the distribution and response of stress components of device channel. In addition, several parametric analyses for the structural dimnesion and material systems of the mainstream and candidate technologies are implemented. To demonstrate the accuracy of the presented model, the calculated results are compared with finite element simulation.
On the other hand, the rapid prognosis ability of the proposed model is performed on Si, Ge, and group III-V based of nanoscaled transistors under specifically designed stressors. The S/D dependence of performance variety for all considered device materials can be directly estimated by changing the designed S/D length substituted into the analytical model. Moreover, the variations in induced mobility gain are further quantified by using corresponding stress-piezoresistance relation and the electrical performances of devices are consequently interpreted. In conclusion, the analytic methodlogy with regard to stress-induced device performance prediction presented in this study is useful to speed up the design period of novel semiconductor devices. All the results shown in this research are expected to be the reference guideline as strained engineering technology is taken into account.

摘要 ---------------------------------------------------I
目錄 ---------------------------------------------------V
表目錄 ------------------------------------------------VIII
圖目錄 -------------------------------------------------XII
第一章 緒論 -------------------------------------------1
1.1 前言 -------------------------------------------1
1.2 研究動機 -------------------------------------------3
1.3 文獻回顧 -------------------------------------------4
1.2.1 提升半導體元件效能之技術 ---------------------------4
1.2.2 應變工程技術於半導體元件的應用 ------------------13
1.2.3 元件力學解析解模型之演進 --------------------------29
1.3 研究目標 ------------------------------------------31
第二章 基礎理論 ----------------------------------33
2.1 基本操作原理與電性效能估算 --------------------------33
2.2 載子遷移率與壓阻效應 --------------------------42
2.3 應變緩衝層與源汲極合金之晶格不匹配應變估算 ----------46
2.4 線彈性有限單元法理論 --------------------------49
第三章 奈米元件之力學解析解推導 --------------------------51
3.1 具應變工程之奈米元件模型與應變效應分析流程 ----------51
3.2 一維MOSFET結構之解析解推導與驗證 ------------------52
3.2.1 一維元件通道方向之解析解 --------------------------54
3.2.2 具不同矽鍺源/汲極濃度之矽基元件其通道應力驗證----------59
3.3 二維MOSFET結構之解析解推導與驗證 ------------------63
3.3.1 二維通道與厚度方向之解析解 --------------------------64
3.3.2 矽基元件通道應力之二維解析解與模擬分析驗證 ----------95
第四章 結果與討論 -----------------------------------------107
4.1 一維解析解對矽、鍺、三五族元件之增益估算結果 ---------107
4.1.1 P型半導體通道區域之應力與載子遷移率 -----------------108
4.1.2 N型半導體通道區域之應力與載子遷移率 -----------------115
4.2 一維解析解與文獻之通道應力值比較 -----------------121
4.3 一維解析解研究分析之結論 -------------------------125
4.4 二維解析解對矽、鍺元件之效能增益估算結果 ---------127
4.4.1 P型半導體通道區域之應力與載子遷移率 -----------------128
4.4.2 N型半導體通道區域之應力與載子遷移率 -----------------134
4.5 二維解析解研究分析之結論 -------------------------139
第五章 結論與未來展望 ---------------------------------141
附錄 -------------------------------------------------144
應變工程元件之電性分析與驗證 -----------------144
參考文獻 -------------------------------------------------163

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