自2007年，Intel導入了金屬閘極與高介電常數閘極氧化層（HKMG）製程，氧化鉿基的閘極氧化層被證明與CMOS製程完全相容。隨著摻雜氧化鉿薄膜所具備的鐵電性質被發現，使得CMOS製程相容且可高度微縮的鐵電電晶體（FeFET）變為可行，由於源自於非中心對稱分子結構所產生的電偶極矩與殘留極化，鐵電電晶體可基於電場的庫倫耦合改變其電導率，展現出不同的高低阻態，作為新型態低功耗且高速切換的記憶體而廣受學術界及業界關注。然而現今大多數的鐵電電晶體都是基於平面式結構，這大幅限制了其在先進製程節點與嵌入式記憶體的應用，因此開發一個與先進製程節點相容的高效能記憶體與電晶體相當重要。本論文主要將應用於超越摩爾定律（More than Moore）之延伸，探討鰭式電晶體結構與鐵電氧化鉿鋯結合之研究，以符合未來高密度與高效能記憶體與電晶體技術的趨勢。本論文共分為三個部分，（一）鐵電氧化鉿鋯鰭式電晶體之非揮發性記憶體，（二）鍺通道雙鰭式電晶體之嵌入式電荷捕捉非揮發記憶體，（三）鐵電氧化鉿鋯負電容溝槽鰭式電晶體。
第一部份（第三至五章）為鐵電氧化鉿鋯鰭式電晶體之非揮發性記憶體研究。首先提出結合鰭式結構與鐵電氧化鉿鋯作為非揮發性記憶體，由於鰭式結構的高電場與堆疊的高介電常數之介面層（interfacial layer），大幅提升了鐵電鰭式電晶體的寫入抹除效率，並達到了奈秒（ns）等級，且同時擁有大的記憶窗口，可以增加多次讀寫的容忍度。在這個部分，同時驗證了高度微縮下，鐵電鰭式電晶體的多位元操作，並證明其具備高密度儲存級與嵌入式記憶體的應用。
第二部份（第六章）設計了雙鰭式電晶體結構之鍺通道電荷捕捉非揮發性記憶體。鍺通道為下世代有望取代矽的候選之一，鍺的高遷移率以及大電流可以增強NAND架構下的讀取電流，有助於記憶體的讀取效率，同時設計了鰭式電晶體結構，不僅相容於16 nm以下的先進製程，受益於鰭式結構的高電場效應，增強了記憶體的寫入抹除效率。同時，雙電晶體的架構不需要如SONOS般堆疊多個閘極與氧化層，使得雙鰭式電晶體之非揮發性記憶體完全相容於先進製程。
第三部分（第七章）為鐵電氧化鉿鋯負電容溝槽鰭式電晶體。鐵電負電容鰭式電晶體已被證明具有低功耗且次臨界擺幅（SS）低於物理極限60 mV/decade，在此基礎上，我們設計了溝槽鰭式結構，此結構有利於增強電場與負電容效應。結合五奈米氧化鉿鋯鐵電層與溝槽鰭式結構，負電容溝槽鰭式電晶體得到比一般負電容鰭式電晶體更陡峭的次臨界擺幅，更大的開電流與開關電流比。

Since 2007, Intel has introduced the High-K Metal Gate (HKMG) process with a hafnium-based gate insulator, which has been proven to be fully compatible with CMOS technology. The discovery of the ferroelectric properties of doped hafnium oxide films has made it feasible to develop ferroelectric field-effect transistors (FeFETs) that are both CMOS-compatible and highly scalable. Due to the electric dipole moment and remnant polarization resulting from the non-centrosymmetric molecular structure, FeFETs can change their conductivity based on electric field-induced Coulomb coupling, exhibiting high and low resistance states. As a result, they have attracted significant attention from the academic and industrial communities as a new type of low-power and high switching speed memory. However, most current FeFETs are based on planar structures, which severely limits their application in advanced technology nodes and embedded memory. Therefore, the development of high-performance memories and transistors that are compatible with advanced technology nodes is crucial.
This dissertation focuses on the extension of beyond-CMOS (More than Moore) technology and explores the combination of fin field-effect transistor (FinFET) structures with ferroelectric hafnium zirconium oxide (HZO) for future trends in high-density and high-performance memory and transistor technologies. The dissertation is divided into three parts:
The first part (Chapters 3 to 5) focuses on the study of ferroelectric HZO FinFET (Fe-FinFET) non-volatile memory. A novel approach combining the FinFET structure with ferroelectric HZO is proposed for non-volatile memory applications. The high electric field of the FinFET structure and the interfacial layer with high dielectric constant greatly enhance the program/erase efficiency of Fe-FinFET, achieving nanosecond-level performance while maintaining a large memory window for improved fault-tolerant of readout. This part also demonstrates the multi-level cell operation of Fe-FinFET at high scaling, highlighting its potential for high-density storage and embedded memory applications.
The second part (Chapter 6) presents the design of germanium twin-transistor charge-trapping-based non-volatile memory with FinFET structure. Germanium channel devices are promising candidates to replace silicon in next-generation technology. The high carrier mobility and large current of germanium enhance the read current in NAND architectures, improving memory read efficiency. The FinFET structure is designed to be compatible with advanced processes below 16 nm technology node, benefiting from the high electric field effect of the FinFET structure to enhance program/erase efficiency. Moreover, the twin-transistor architecture eliminates the need for multiple stacked gates and oxide layers like SONOS, making the twin FinFET-based non-volatile memory fully compatible with advanced processes.
The third part (Chapter 7) focuses on ferroelectric HZO negative-capacitance trench FinFETs. Ferroelectric negative-capacitance FinFETs have been demonstrated to exhibit low power consumption and subthreshold swing (SS) below the physical limit of 60 mV/decade. Building upon this, a trench FinFET structure is designed to further enhance the electric field and negative-capacitance effect. By combining a 5 nm HZO with the trench FinFET structure, the negative-capacitance trench FinFET achieves a steeper SS and higher on–off current ratio compared to conventional negative-capacitance FinFETs.

中 文 摘 要 i
Abstract iii
Acknowledgment vi
Table of Contents vii
List of Tables xi
List of Figures xii
Chapter 1 Introduction 1
1.1 Non-Volatile Memory 1
1.2 Challenges and Development of Non-Volatile Memory 2
1.3 Device Scaling Challenges and Future Perspectives 5
1.4 Fin Field-Effect Transistor (FinFET) 8
1.5 Organization of the Dissertation 11
1.6 References 13
Chapter 2 Origins of Ferroelectric Field-Effect Transistor 17
2.1 Ferroelectricity in Hafnium Oxide 17
2.2 Ferroelectric Field-Effect Transistor (FeFET) Memory 21
2.2.1 Operation Principles 21
2.2.2 Switching Mechanism and Read Operation 25
2.2.3 Charge-Trapping Induced Underestimated Memory Window 29
2.2.4 Interfacial Layer Influenced Endurance 31
2.2.5 Advantages and Future Prospects of FeFET 32
2.3 Ferroelectric Negative Capacitance (NC) Field-Effect Transistor 34
2.4 References 37
Chapter 3 High Speed and Large Memory Window Ferroelectric HfZrO2 FinFET for High-Density Nonvolatile Memory 43
3.1 Motivation and Literature Review 43
3.2 Experimental 44
3.3 Results and Discussion 45
3.4 Summary 57
3.5 References 58
Chapter 4 Multilevel Cell Ferroelectric HfZrO2 FinFET with High Speed and Large Memory Window using AlON Interfacial Layer 63
4.1 Motivation and Literature Review 63
4.2 Experimental 65
4.3 Results and Discussion 65
4.4 Summary 76
4.5 References 77
Chapter 5 HfO2/ZrO2 Superlattice Dielectric and High k AlON Interfacial Layer for Ferroelectric FinFETs 82
5.1 Motivation and Literature Review 82
5.2 Experimental 84
5.3 Results and Discussion 84
5.4 Summary 94
5.5 References 95
Chapter 6 Germanium Twin-Transistor Nonvolatile Memory with FinFET Structure 98
6.1 Motivation and Literature Review 98
6.2 Experimental 100
6.3 Results and Discussion 102
6.4 Summary 109
6.5 References 110
Chapter 7 Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application 115
7.1 Motivation and Literature Review 115
7.2 Experimental 117
7.3 Results and Discussion 119
7.4 Summary 134
7.5 References 135
Chapter 8 Conclusion 140
Curriculum Vitae 142
Publication List 143
Appendix 146

[1.1] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, "Novel multi-bit SONOS type flash memory using a high-k charge trapping layer," 2003 Symposium on VLSI Technology, pp. 27-28.
[1.2] C. Tung-Sheng, W. Kuo-Hong, C. Hsien, and K. Chin-Hsing, “Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer,” IEEE Electron Device Letters, vol. 25, no. 4, pp. 205-207, 2004.
[1.3] Emerging Non-Volatile Memory 2021, Yole Développement, February 2021.
[1.4] Ferroelectric Memory Company © [https://ferroelectric-memory.com/].
[1.5] S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, and M. T. Bohr, “In Search of “Forever,” Continued Transistor Scaling One New Material at a Time,” IEEE Transactions on Semiconductor Manufacturing, vol. 18, no. 1, pp. 26-36, 2005.
[1.6] Meikei Ieong, Bruce Doris, Jakub Kedzierski, Ken Rim, and Min Yang, “Silicon Device Scaling to the Sub-10-nm Regime,” Science, vol. 306, no. 5704, pp. 2057-2060, 2004.
[1.7] T. Y. Chan, P. K. Ko, and C. Hu, “Dependence of channel electric field on device scaling,” IEEE Electron Device Letters, vol. 6, no. 10, pp. 551-553, 1985.
[1.8] Peter J. Denning, and Ted G. Lewis, “Exponential laws of computing growth,” Communications of the ACM, vol. 60, no. 1, pp. 54-65, 2016.
[1.9] G. E. Moore, “Cramming More Components Onto Integrated Circuits,” Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, 1998.
[1.10] R. R. Schaller, “Moore's law: past, present and future,” IEEE Spectrum, vol. 34, no. 6, pp. 52-59, 1997.
[1.11] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and Wong Hon-Sum Philip, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of the IEEE, vol. 89, no. 3, pp. 259-288, 2001.
[1.12] K. J. Kuhn, "Moore's Law Past 32nm: Future Challenges in Device Scaling," 2009 13th International Workshop on Computational Electronics, pp. 1-6.
[1.13] K. Ronse, P. De Bisschop, G. Vandenberghe, E. Hendrickx, R. Gronheid, A. V. Pret, A. Mallik, D. Verkest, and A. Steegen, "Opportunities and challenges in device scaling by the introduction of EUV lithography," 2012 International Electron Devices Meeting, pp. 18.5.1-18.5.4.
[1.14] A. Pirovano, A. L. Lacaita, and A. S. Spinelli, “Two-dimensional quantum effects in nanoscale MOSFETs,” IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 25-31, 2002.
[1.15] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling," 1987 International Electron Devices Meeting, pp. 718-721.
[1.16] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, 2003.
[1.17] International Roadmap for Devices and Systems (IRDS™) 2022 Edition. [Online]. Available: https://irds.ieee.org/editions/2022
[1.18] D. Hisamoto, L. Wen-Chin, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, K. Tsu-Jae, J. Bokor, and H. Chenming, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000.
[1.19] IEEE Spectrum. [Online]. Available: https://spectrum.ieee.org/
[1.20] H. J. Lee, S. Rami, S. Ravikumar, V. Neeli, K. Phoa, B. Sell, and Y. Zhang, "Intel 22nm FinFET (22FFL) Process Technology for RF and mm Wave Applications and Circuit Design Optimization for FinFET Technology," 2018 IEEE International Electron Devices Meeting (IEDM), pp. 14.1.1-14.1.4.
[1.21] G. Yeap, S. S. Lin, Y. M. Chen, H. L. Shang, P. W. Wang, H. C. Lin, Y. C. Peng, J. Y. Sheu, M. Wang, X. Chen, B. R. Yang, C. P. Lin, F. C. Yang, Y. K. Leung, D. W. Lin, C. P. Chen, K. F. Yu, D. H. Chen, C. Y. Chang, H. K. Chen, P. Hung, C. S. Hou, Y. K. Cheng, J. Chang, L. Yuan, C. K. Lin, C. C. Chen, Y. C. Yeo, M. H. Tsai, H. T. Lin, C. O. Chui, K. B. Huang, W. Chang, H. J. Lin, K. W. Chen, R. Chen, S. H. Sun, Q. Fu, H. T. Yang, H. T. Chiang, C. C. Yeh, T. L. Lee, C. H. Wang, S. L. Shue, C. W. Wu, R. Lu, W. R. Lin, J. Wu, F. Lai, Y. H. Wu, B. Z. Tien, Y. C. Huang, L. C. Lu, J. He, Y. Ku, J. Lin, M. Cao, T. S. Chang, and S. M. Jang, "5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications," 2019 IEEE International Electron Devices Meeting (IEDM), pp. 36.7.1-36.7.4.
[1.22] J. C. Liu, S. Mukhopadhyay, A. Kundu, S. H. Chen, H. C. Wang, D. S. Huang, J. H. Lee, M. I. Wang, R. Lu, S. S. Lin, Y. M. Chen, H. L. Shang, P. W. Wang, H. C. Lin, G. Yeap, and J. He, "A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application," 2020 IEEE International Electron Devices Meeting (IEDM), pp. 9.2.1-9.2.4.
[2.1] R. C. Garvie, “The Occurrence of Metastable Tetragonal Zirconia as a Crystallite Size Effect,” The Journal of Physical Chemistry, vol. 69, no. 4, pp. 1238-1243, 1965/04/01, 1965.
[2.2] J. Wang, H. P. Li, and R. Stevens, “Hafnia and hafnia-toughened ceramics,” Journal of Materials Science, vol. 27, no. 20, pp. 5397-5430, 1992/10/01, 1992.
[2.3] R. D. Clark, “Ferroelectric HfZrO Films: Process, Characterization and Devices”, 03-Oct-2018. [Online]. Available: ecsarxiv.org/qtxnd
[2.4] M. E. Lines and A. M. Glass Principles and Applications of Ferroelectrics and Related Materials. (Oxford University Press, Oxford, England, 2001), Vol. 1.
[2.5] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide thin films,” Appl. Phys. Lett., vol. 99, no. 10, 2011, Art. no. 102903, doi: 10.1063/1.3634052.
[2.6] E. Yurchuk, J. Müller, J. Paul, T. Schlösser, D. Martin, R. Hoffmann, S. Mueller, S. Slesazeck, U. Schröeder, R. Boschke, R. van Bentum, and T. Mikolajick, “Impact of scaling on the performance of HfO2-based ferroelectric field effect transistors,” IEEE Trans. Electron Devices, vol. 61, no. 11, pp. 3699–3706, Nov. 2014, doi: 10.1109/TED.2014.2354833.
[2.7] S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder, and T. Mikolajick, “Incipient ferroelectricity in Al-doped HfO2 thin films,” Adv. Funct. Mater., vol. 22, no. 11, pp. 2412–2417, Jun. 2012, doi: 10.1002/adfm.201103119.
[2.8] T. P. Juan, C. Chang, and J. Y. Lee, “A new metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (Dy2O3)-semiconductor (MFIS) FET for nonvolatile memory applications,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 217–220, Apr. 2006, doi: 10.1109/LED.2006.870414.
[2.9] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors,” in IEDM Tech. Dig., Dec. 2011, pp. 24.5.1–24.5.4, doi: 10.1109/IEDM.2011.6131606.
[2.10] L. Xu, T. Nishimura, S. Shibayama, T. Yajima, S. Migita, and A. Toriumi, “Kinetic pathway of the ferroelectric phase formation in doped HfO2 films,” Journal of Applied Physics, vol. 122, no. 12, pp. 124104, 2017.
[2.11] I. Fina, and F. Sánchez, “Epitaxial Ferroelectric HfO2 Films: Growth, Properties, and Devices,” ACS Applied Electronic Materials, vol. 3, no. 4, pp. 1530-1549, 2021/04/27, 2021.
[2.12] S. Estandía, N. Dix, J. Gazquez, I. Fina, J. Lyu, M. F. Chisholm, J. Fontcuberta, and F. Sánchez, “Engineering Ferroelectric Hf0.5Zr0.5O2 Thin Films by Epitaxial Stress,” ACS Applied Electronic Materials, vol. 1, no. 8, pp. 1449-1457, 2019/08/27, 2019.
[2.13] Ferroelectric Memory Company © [https://ferroelectric-memory.com/].
[2.14] K. Ni, P. Sharma, J. Zhang, M. Jerry, J.A. Smith, K.Tapily, R. Clark, S. Mahapatra, and S. Datta, “Critical role of interlayer in Hf0.5Zr0.5O2 ferroelectric FET nonvolatile memory performance,” IEEE Trans. Electron Devices, vol. 65, no. 6, pp. 2461–2469, Jun. 2018, doi: 10.1109/TED.2018.2829122.
[2.15] T. Ali, P. Polakowski, S. Riedel, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, K. Seidel, D. Löhr, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, J. Calvo, K. Zimmermann, and J. Müller, “High endurance ferroelectric hafnium oxide-based FeFET memory without retention penalty,” IEEE Trans. Electron Devices, vol. 65, no. 9, pp. 3769–3774, Sep. 2018, doi: 10.1109/TED.2018. 2856818.
[2.16] S. L. Miller and P. J. McWhorter, “Physics of the ferroelectric nonvolatile memory field effect transistor,” J. Appl. Phys., vol. 72, no. 12, pp. 5999–6010, Dec. 1992, doi: 10.1063/1.351910.
[2.17] S. L. Miller, and P. J. McWhorter, “Physics of the ferroelectric nonvolatile memory field effect transistor,” Journal of Applied Physics, vol. 72, no. 12, pp. 5999-6010, 1992.
[2.18] L. Hang-Ting, W. Chien-Jang, and T. Tseung-Yuen, “Device modeling of ferroelectric memory field-effect transistor (FeMFET),” IEEE Transactions on Electron Devices, vol. 49, no. 10, pp. 1790-1798, 2002.
[2.19] K.-T. Chen, H.-Y. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, M.-H. Liao, K.-S. Li, S.-T. Chang, and M.-H. Lee, “Non-volatile ferroelectric FETs using 5-nm Hf0.5Zr0.5O2 with high data retention and read endurance for 1T memory applications,” IEEE Electron Device Lett., vol. 40, no. 3, pp. 399–402, Mar. 2019, doi: 10.1109/LED.2019.2896231.
[2.20] A. J. Tan, Y. H. Liao, L. C. Wang, N. Shanker, J. H. Bae, C. Hu, and S. Salahuddin, “Ferroelectric HfO2 memory transistors with high-k interfacial layer and write endurance exceeding 1010 cycles,” IEEE Electron Device Lett., vol. 42, no. 7, pp. 994-997, Jul. 2021, doi: 10.1109/LED.2021.3083219.
[2.21] H.-K. Peng, T.-H. Kao, Y.-C. Kao, P.-J. Wu, and Y.-H. Wu, “Reduced Asymmetric Memory Window Between Si-Based n- and p-FeFETs With Scaled Ferroelectric HfZrOx and AlON Interfacial Layer,” IEEE Electron Device Lett., vol. 42, no. 6, pp. 835-838, Jun. 2021, doi: 10.1109/LED.2021.3074434.
[2.22] S. Mueller, S. R. Summerfelt, J. Muller, U. Schroeder, and T. Mikolajick, “Ten-Nanometer Ferroelectric Si: HfO2 Films for Next-Generation FRAM Capacitors,” IEEE Electron Device Letters, vol. 33, no. 9, pp. 1300-1302, 2012.
[2.23] J. Muller, T. S. Boscke, U. Schroder, R. Hoffmann, T. Mikolajick, and L. Frey, “Nanosecond Polarization Switching and Long Retention in a Novel MFIS-FET Based on Ferroelectric HfO2” IEEE Electron Device Letters, vol. 33, no. 2, pp. 185-187, 2012.
[2.24] Alexander K. Tagantsev, Igor Stolichnov, Nava Setter, Jeffrey S. Cross, and Mineharu Tsukada, “Non-Kolmogorov-Avrami switching kinetics in ferroelectric thin films,” Physical Review B, vol. 66, no. 21, pp. 214109, 12/23/, 2002.
[2.25] Halid Mulaosmanovic, Johannes Ocker, Stefan Müller, Uwe Schroeder, Johannes Müller, Patrick Polakowski, Stefan Flachowsky, Ralf van Bentum, Thomas Mikolajick, and Stefan Slesazeck, “Switching Kinetics in Nanoscale Hafnium Oxide Based Ferroelectric Field-Effect Transistors,” ACS Applied Materials & Interfaces, vol. 9, no. 4, pp. 3792-3798, 2017/02/01, 2017.
[2.26] H. Mulaosmanovic, S. Dünkel, M. Trentzsch, S. Beyer, E. T. Breyer, T. Mikolajick, and S. Slesazeck, “Investigation of Accumulative Switching in Ferroelectric FETs: Enabling Universal Modeling of the Switching Behavior,” IEEE Transactions on Electron Devices, vol. 67, no. 12, pp. 5804-5809, 2020.
[2.27] H. Mulaosmanovic, S. Dünkel, J. Muller, M. Trentzsch, S. Beyer, E. T. Breyer, T. Mikolajick, and S. Slesazeck, “Impact of read operation on the performance of HfO2-based ferroelectric FETs,” IEEE Electron Device Lett., vol. 41, no. 9, pp. 1420–1423, Sep. 2020, doi: 10.1109/LED.2020.3007220.
[2.28] H. Mulaosmanovic, E. T. Breyer, T. Mikolajick, and S. Slesazeck, "Switching and Charge Trapping in HfO2-based Ferroelectric FETs: An Overview and Potential Applications," 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 1-4.
[2.29] E. Yurchuk, J. Müller, S. Müller, J. Paul, M. Pešić, R. v. Bentum, U. Schroeder, and T. Mikolajick, “Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories,” IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3501-3507, 2016.
[2.30] H. Mulaosmanovic, E. T. Breyer, S. Dünkel, S. Beyer, T. Mikolajick, and S. Slesazeck, “Ferroelectric field-effect transistors based on HfO2: A review,” Nanotechnology, vol. 32, Sep. 2021, Art. no. 502002, doi: 10.1088/1361-6528/ac189f.
[2.31] E. Yurchuk, S. Mueller, D. Martin, S. Slesazeck, U. Schroeder, T. Mikolajick, J. Müller, J. Paul, R. Hoffmann, J. Sundqvist, T. Schlösser, R. Boschke, R. V. Bentum, and M. Trentzsch, “Origin of the endurance degradation in the novel HfO2-based 1T ferroelectric non-volatile memories,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Jun. 2014, pp. 2E.5.1–2E.5.5, doi: 10.1109/IRPS.2014.6860603.
[2.32] K. Florent, M. Pesic, A. Subirats, K. Banerjee, S. Lavizzari, A. Arreghini, L. D. Piazza, G. Potoms, F. Sebaai, S. R. C. Mcmitchell, M. Popovici, G. Groeseneken, and J. Van Houdt, “Vertical ferroelectric HfO2 FET based on 3-D NAND architecture: Towards dense low-power memory,” in IEDM Tech. Dig., Dec. 2018, pp. 2.5.1–2.5.4, doi: 10.1109/IEDM.2018.8614710.
[2.33] Muhammad A. Alam (2015), "A Tutorial Introduction to Negative-Capacitor Landau Transistors: Perspectives on the Road Ahead," https://nanohub.org/resources/23157.
[2.34] H. Amrouch, G. Pahwa, A. D. Gaidhane, J. Henkel, and Y. S. Chauhan, “Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance,” IEEE Access, vol. 6, pp. 52754-52765, 2018.
[3.1] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide thin films,” Appl. Phys. Lett., vol. 99, no. 10, 2011, Art. no. 102903, doi: 10.1063/1.3634052.
[3.2] E. Yurchuk, J. Müller, J. Paul, T. Schlösser, D. Martin, R. Hoffmann, S. Mueller, S. Slesazeck, U. Schröeder, R. Boschke, R. van Bentum, and T. Mikolajick, “Impact of scaling on the performance of HfO2-based ferroelectric field effect transistors,” IEEE Trans. Electron Devices, vol. 61, no. 11, pp. 3699–3706, Nov. 2014, doi: 10.1109/TED.2014.2354833.
[3.3] S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder, and T. Mikolajick, “Incipient ferroelectricity in Al-doped HfO2 thin films,” Adv. Funct. Mater., vol. 22, no. 11, pp. 2412–2417, Jun. 2012, doi: 10.1002/adfm.201103119.
[3.4] T. P. Juan, C. Chang, and J. Y. Lee, “A new metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (Dy2O3)-semiconductor (MFIS) FET for nonvolatile memory applications,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 217–220, Apr. 2006, doi: 10.1109/LED.2006.870414.
[3.5] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors,” in IEDM Tech. Dig., Dec. 2011, pp. 24.5.1–24.5.4, doi: 10.1109/IEDM.2011.6131606.
[3.6] S. Dünkel, M. Trentzsch, R. Richter, P. Moll, C. Fuchs, O. Gehring, M. Majer, S. Wittek, B. Muller, T. Melde, H. Mulaosmanovic, S. Slesazeck, S. Müller, J. Ocker, M. Noack, D.-A. Lohr, P. Polakowski, J. Muller, T. Mikolajick, J. Hontschel, B. Rice, J. Pellerin, and S. Beyer,“A FeFET based super-low-power ultra-fast embedded NVM technology for 22 nm FDSOI and beyond,” in IEDM Tech. Dig., Dec. 2017, pp. 19.7.1–19.7.4, doi: 10.1109/IEDM.2017.8268425.
[3.7] M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu, and S. Datta, “Ferroelectric FET analog synapse for acceleration of deep neural network training,” in IEDM Tech. Dig., pp. 6.2.1–6.2.4, Dec. 2017, doi: 10.1109/IEDM.2017.8268338.
[3.8] M. Trentzsch, S. Flachowsky, R. Richter, J. Paul, B. Reimer, D. Utess, S. Jansen, H. Mulaosmanovic, S. Müller, S. Slesazeck, J. Ocker, M. Noack, J. Müller, P. Polakowski, J. Schreiter, S. Beyer, T. Mikolajick, and B. Rice, “A 28 nm HKMG super low power embedded NVM technology based on ferroelectric FETs,” in IEDM Tech. Dig., 2016, pp. 11.5.1–11.5.4, doi: 10.1109/IEDM.2016.7838397.
[3.9] H. Mulaosmanovic, J. Ocker, S. Müller, U. Schroeder, J. Müller, P. Polakowski, S. Flachowsky, R. van Bentum, T. Mikolajick, and S. Slesazeck, “Switching kinetics in nanoscale hafnium oxide based ferroelectric field-effect transistors,” ACS Appl. Mater. Interfaces, vol. 9, no. 4, pp. 3792–3798, 2017, doi: 10.1021/acsami.6b13866.
[3.10] J. Mohan, H. Hernandez-Arriaga, Y. C. Jung, T. Onaya, C. -Y. Nam, E. H. R. Tsai, S. J. Kim, and J. Kim, “Ferroelectric polarization retention with scaling of Hf0.5Zr0.5O2 on silicon,” Appl. Phys. Lett., vol. 118, no. 10, Mar. 2021, Art. no. 102903, doi: 10.1063/ 5.0035579.
[3.11] T. Ali, P. Polakowski, S. Riedel, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, K. Seidel, D. Löhr, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, J. Calvo, K. Zimmermann, and J. Müller, “High endurance ferroelectric hafnium oxide-based FeFET memory without retention penalty,” IEEE Trans. Electron Devices, vol. 65, no. 9, pp. 3769–3774, Sep. 2018, doi: 10.1109/TED.2018. 2856818.
[3.12] K. Chatterjee, S. Kim, G. Karbasian, A. J. Tan, A. K. Yadav, A. I. Khan, C. Hu, and S. Salahuddin, “Self-aligned, gate last, FDSOI, ferroelectric gate memory device with 5.5-nm Hf0.8Zr0.2O2, high endurance and breakdown recovery,” IEEE Electron Device Lett., vol. 38, no. 10, pp. 1379–1382, Oct. 2017, doi: 10.1109/LED.2017.2748992.
[3.13] K.-T. Chen, H.-Y. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, M.-H. Liao, K.-S. Li, S. T. Chang, and M. H. Lee, “Non-volatile ferroelectric FETs using 5-nm Hf0.5Zr0.5O2 with high data retention and read endurance for 1T memory applications,” IEEE Electron Device Lett., vol. 40, no. 3, pp. 399–402, Mar. 2019, doi: 10.1109/LED.2019.2896231.
[3.14] J. Müller, E. Yurchuk, T. Schlösser, J. Paul, R. Hoffmann, S. Müller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kücher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schröder, and T. Mikolajick, “Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG,” in Proc. Symp. VLSI Technol. (VLSIT), Jun. 2012, pp. 25–26, doi: 10.1109/VLSIT.2012.6242443.
[3.15] J.-H. Bae, D. Kwon, N. Jeon, S. Cheema, A. J. Tan, C. Hu, and S. Salahuddin, “Highly scaled, high endurance, Ω-gate, nanowire ferroelectric FET memory transistors,” IEEE Electron Device Lett., vol. 41, no. 11, pp. 1637–1640, Nov. 2020, doi: 10.1109/LED.2020.3028339.
[3.16] H.-K. Peng, C.-Y. Chan, K.-Y. Chen, and Y.-H. Wu, “Enabling large memory window and high reliability for FeFET memory by integrating AlON interfacial layer,” Appl. Phys. Lett., vol. 118, no. 10, Mar. 2021, Art. no. 103503, doi: 10.1063/5.0036824.
[3.17] K. Florent, M. Pesic, A. Subirats, K. Banerjee, S. Lavizzari, A. Arreghini, L. D. Piazza, G. Potoms, F. Sebaai, S. R. C. Mcmitchell, M. Popovici, G. Groeseneken, and J. Van Houdt, “Vertical ferroelectric HfO2 FET based on 3-D NAND architecture: Towards dense low-power memory,” in IEDM Tech. Dig., Dec. 2018, pp. 2.5.1–2.5.4, doi: 10.1109/IEDM.2018.8614710.
[3.18] H. Mulaosmanovic, E. T. Breyer, T. Mikolajick, and S. Slesazeck, “Ferroelectric FETs with 20-nm-thick HfO2 layer for large memory window and high performance,” IEEE Trans. Electron Devices, vol. 66, no. 9, pp. 3828–3833, Sep. 2019, doi: 10.1109/TED.2019.2930749.
[3.19] Sentaurus TCAD Version 2016, Synop., Mountain View, CA, USA, 2016.
[3.20] H. Mulaosmanovic, S. Dünkel, J. Muller, M. Trentzsch, S. Beyer, E. T. Breyer, T. Mikolajick, and S. Slesazeck, “Impact of read operation on the performance of HfO2-based ferroelectric FETs,” IEEE Electron Device Lett., vol. 41, no. 9, pp. 1420–1423, Sep. 2020, doi: 10.1109/LED.2020.3007220.
[3.21] S.-C. Yan, C.-J. Sun, M.-J. Tsai, L.-C. Chen, M.-S. Yeh, C.-C. Li, Y.-J. Lee, and Y.-C. Wu, “Germanium twin-transistor nonvolatile memory with FinFET structure,” IEEE J. Electron Devices Soc., vol.8, pp. 589–593, 2020, doi: 10.1109/JEDS.2020.2999616.
[3.22] C.-Y. Chan, K.-Y. Chen, H.-K. Peng, and Y.-H. Wu, “FeFET memory featuring large memory window and robust endurance of long pulse cycling by interface engineering using high-k AlON,” in Proc. IEEE Symp. VLSI Technol., Jun. 2020, pp. 1–2, doi: 10.1109/ VLSITechnology18217.2020.9265103.
[3.23] K. Ni, P. Sharma, J. Zhang, M. Jerry, J.A. Smith, K.Tapily, R. Clark, S. Mahapatra, and S. Datta, “Critical role of interlayer in Hf0.5Zr0.5O2 ferroelectric FET nonvolatile memory performance,” IEEE Trans. Electron Devices, vol. 65, no. 6, pp. 2461–2469, Jun. 2018, doi: 10.1109/TED.2018.2829122.
[4.1] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide thin films,” Appl. Phys. Lett., vol. 99, no. 10, Sep. 2011, Art. no. 102903, doi: 10.1063/1.3634052.
[4.2] M. Trentzsch, S. Flachowsky, R. Richter, J. Paul, B. Reimer, D. Utess, S. Jansen, H. Mulaosmanovic, S. M´’uller, S. Slesazeck, J. Ocker, M. Noack, J. Müller, P. Polakowski, J. Schreiter, S. Beyer, T. Mikolajick, and B. Rice, “A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs,” in IEDM Tech. Dig., Dec. 2016, p. 11, doi: 10.1109/IEDM.2016.7838397.
[4.3] E. T. Breyer, H. Mulaosmanovic, T. Mikolajick, and S. Slesazeck, “Reconfigurable NAND/NOR logic gates in 28 nm HKMG and 22 nm FD-SOI FeFET technology,” in IEDM Tech. Dig., Dec. 2017, p. 28, doi: 10.1109/IEDM.2017.8268471.
[4.4] F. Mo, Y. Tagawa, C. Jin, M. Ahn, T. Saraya, T. Hiramoto, and M. Kobayashi, “Experimental demonstration of ferroelectric HfO2 FET with ultrathin-body IGZO for high-density and low-power memory application,” in Proc. Symp. VLSI Technol., Jun. 2019, pp. T42–T43, doi: 10.23919/VLSIT.2019.8776553.
[4.5] S. Slesazeck, U. Schroeder, and T. Mikolajick, “Embedding hafnium oxide based FeFETs in the memory landscape,” in Proc. Int. Conf. IC Design Technol. (ICICDT), Jun. 2018, pp. 121–124, doi: 10.1109/ICICDT. 2018.8399771.
[4.6] S. Dutta, A. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, and S. Datta, “Biologically plausible ferroelectric quasi-leaky integrate and fire neuron,” in Proc. Symp. VLSI Technol., Jun. 2019, pp. T140–T141, doi: 10.23919/VLSIT.2019.8776487.
[4.7] K. Ni, B. Grisafe, W. Chakraborty, A. K. Saha, S. Dutta, M. Jerry, J. A. Smith, S. Gupta, and S. Datta, “In-memory computing primitive for sensor data fusion in 28 nm HKMG FeFET technology,” in IEDM Tech. Dig., Dec. 2018, p. 16, doi: 10.1109/IEDM.2018.8614527.
[4.8] K. Ni, S. Dutta, and S. Datta, “Ferroelectrics: From memory to computing,” in Proc. 25th Asia South Pacific Design Autom. Conf. (ASP-DAC), Jan. 2020, pp. 401–406, doi: 10.1109/ASP-DAC47756.2020.9045150.
[4.9] C.-Y. Liao, K.-Y. Hsiang, F.-C. Hsieh, S.-H. Chiang, S.-H. Chang, J.-H. Liu, C.-F. Lou, C.-Y. Lin, T.-C. Chen, C.-S. Chang, and M. H. Lee, “Multibit ferroelectric FET based on nonidentical double HfZrO2 for high-density nonvolatile memory,” IEEE Electron Device Lett., vol. 42, no. 4, pp. 617–620, Apr. 2021, doi: 10.1109/LED.2021.3060589.
[4.10] H.-K. Peng, C.-M. Liu, Y.-C. Kao, P.-J. Wu, and Y.-H. Wu, “Improved immunity to sub-cycling induced instability for triple-level cell ferroelectric FET memory by depositing HfZrOx on NH3 plasma-treated Si,” IEEE Electron Device Lett., vol. 43, no. 8, pp. 1219–1222, Aug. 2022, doi: 10.1109/LED.2022.3185000.
[4.11] C. Li, F. Müller, T. Ali, R. Olivo, M. Imani, S. Deng, C. Zhuo, T. Kampfe, X. Yin, and K. Ni, “A scalable design of multi-bit ferroelectric content addressable memory for data-centric computing,” in IEDM Tech. Dig., Dec. 2020, p. 29, doi: 10.1109/IEDM13553.2020.9372119.
[4.12] T. Ali, P. Polakowski, K. Kuhnel, M. Czernohorsky, T. Kampfe, M. Rudolph, B. Patzold, D. Lehninger, F. M´’uller, R. Olivo, M. Lederer, R. Hoffmann, P. Steinke, K. Zimmermann, U. Muhle, K. Seidel, and J. Müller, “A multilevel FeFET memory device based on laminated HSO and HZO ferroelectric layers for high-density storage,” in IEDM Tech. Dig., Dec. 2019, p. 28, doi: 10.1109/IEDM19573.2019.8993642.
[4.13] T. Ali, K. Mertens, R. Olivo, M. Rudolph, S. Oehler, K. Kuhnel, D. Lehninger, F. M´’uller, M. Lederer, R. Hoffmann, P. Schramm, K. Biedermann, A. M. Kia, J. Metzger, R. Binder, M. Czernohorsky, T. Kampfe, J. Müller, K. Seidel, J. V. Houdt, and L. M. Eng, “A novel hybrid high-speed and low power antiferroelectric HSO boosted charge trap memory for high-density storage,” in IEDM Tech. Dig., Dec. 2020, p. 18, doi: 10.1109/IEDM13553.2020.9371980.
[4.14] S.-C. Yan, G.-M. Lan, C.-J. Sun, Y.-H. Chen, C.-H. Wu, H.-K. Peng, Y.-H. Lin, Y.-H. Wu, and Y.-C. Wu, “High speed and large memory window ferroelectric HfZrO2 FinFET for high-density nonvolatile memory,” IEEE Electron Device Lett., vol. 42, no. 9, pp. 1307–1310, Sep. 2021, doi: 10.1109/LED.2021.3097777.
[4.15] C.-Y. Chan, K.-Y. Chen, H.-K. Peng, and Y.-H. Wu, “FeFET memory featuring large memory window and robust endurance of long-pulse cycling by interface engineering using high-k AlON,” in Proc. IEEE Symp. VLSI Technol., Jun. 2020, pp. 1–2, doi: 10.1109/VLSITechnology18217.2020.9265103.
[4.16] H.-K. Peng, T.-C. Lai, T.-H. Kao, and Y.-H. Wu, “Improved reliability and read latency under radiation observed in HfZrOx based p-FeFETs with AlON interfacial layer,” IEEE Electron Device Lett., vol. 43, no. 3, pp. 494–497, Mar. 2022, doi: 10.1109/LED.2022.3147724.
[4.17] H. Mulaosmanovic, S. Slesazeck, J. Ocker, M. Pesic, S. Müller, S. Flachowsky, J. Müller, P. Polakowski, J. Paul, S. Jansen, S. Kolodinski, C. Richter, S. Piontek, T. Schenk, A. Kersch, C. Kunneth, R. van Bentum, U. Schroder, and T. Mikolajick, “Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multilevel FeFET memory cells,” in IEDM Tech. Dig., Dec. 2015, p. 26, doi: 10.1109/IEDM.2015.7409777.
[4.18] H. Mulaosmanovic, J. Ocker, S. Müller, U. Schroeder, J. Müller, P. Polakowski, S. Flachowsky, R. van Bentum, T. Mikolajick, and S. Slesazeck, “Switching kinetics in nanoscale hafnium oxide based ferroelectric field-effect transistors,” ACS Appl. Mater. Interfaces, vol. 9, no. 4, pp. 3792–3798, Feb. 2017, doi: 10.1021/acsami.6b13866.
[4.19] A. I. Khan, A. Keshavarzi, and S. Datta, “The future of ferroelectric field-effect transistor technology,” Nature Electron., vol. 3, no. 10, pp. 588–597, Oct. 2020, doi: 10.1038/s41928-020-00492-7.
[4.20] N. Gong and T.-P. Ma, “A study of endurance issues in HfO2-based ferroelectric field effect transistors: Charge trapping and trap generation,” IEEE Electron Device Lett., vol. 39, no. 1, pp. 15–18, Jan. 2018, doi: 10.1109/LED.2017.2776263.
[4.21] H. Mulaosmanovic, E. T. Breyer, S. Dünkel, S. Beyer, T. Mikolajick, and S. Slesazeck, “Ferroelectric field-effect transistors based on HfO2: A review,” Nanotechnology, vol. 32, Sep. 2021, Art. no. 502002, doi: 10.1088/1361-6528/ac189f.
[4.22] E. Yurchuk, S. Mueller, D. Martin, S. Slesazeck, U. Schroeder, T. Mikolajick, J. Müller, J. Paul, R. Hoffmann, J. Sundqvist, T. Schlösser, R. Boschke, R. V. Bentum, and M. Trentzsch, “Origin of the endurance degradation in the novel HfO2-based 1T ferroelectric non-volatile memories,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Jun. 2014, pp. 2E.5.1–2E.5.5, doi: 10.1109/IRPS.2014.6860603.
[5.1] J.-H. Bae, D. Kwon, N. Jeon, S. Cheema, A. J. Tan, C. Hu, and S. Salahuddin, “Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors,” IEEE Electron Device Letters, vol. 41, no. 11, pp. 1637-1640, 2020.
[5.2] K. T. Chen, H. Y. Chen, C. Y. Liao, G. Y. Siang, C. Lo, M. H. Liao, K. S. Li, S. T. Chang, and M. H. Lee, “Non-Volatile Ferroelectric FETs Using 5-nm Hf0.5Zr0.5O2 With High Data Retention and Read Endurance for 1T Memory Applications,” IEEE Electron Device Letters, vol. 40, no. 3, pp. 399-402, 2019.
[5.3] C. Y. Chan, K. Y. Chen, H. K. Peng, and Y. H. Wu, "FeFET Memory Featuring Large Memory Window and Robust Endurance of Long-Pulse Cycling by Interface Engineering using High-k AlON," 2020 IEEE Symposium on VLSI Technology, pp. 1-2.
[5.4] H.-K. Peng, C.-Y. Chan, K.-Y. Chen, and Y.-H. Wu, “Enabling large memory window and high reliability for FeFET memory by integrating AlON interfacial layer,” Applied Physics Letters, vol. 118, no. 10, 2021.
[5.5] H.-K. Peng, T.-H. Kao, Y.-C. Kao, P.-J. Wu, and Y.-H. Wu, “Reduced Asymmetric Memory Window Between Si-Based n- and p-FeFETs With Scaled Ferroelectric HfZrOₓ and AlON Interfacial Layer,” IEEE Electron Device Letters, vol. 42, no. 6, pp. 835-838, 2021.
[5.6] H. Mulaosmanovic, E. T. Breyer, S. Dunkel, S. Beyer, T. Mikolajick, and S. Slesazeck, “Ferroelectric field-effect transistors based on HfO2: a review,” Nanotechnology, vol. 32, no. 50, Sep 22, 2021.
[5.7] E. Yurchuk, S. Mueller, D. Martin, S. Slesazeck, U. Schroeder, T. Mikolajick, J. Müller, J. Paul, R. Hoffmann, J. Sundqvist, T. Schlösser, R. Boschke, R. v. Bentum, and M. Trentzsch, "Origin of the endurance degradation in the novel HfO2-based 1T ferroelectric non-volatile memories," 2014 IEEE International Reliability Physics Symposium, pp. 2E.5.1-2E.5.5.
[5.8] S.-C. Yan, G.-M. Lan, C.-J. Sun, Y.-H. Chen, C.-H. Wu, H.-K. Peng, Y.-H. Lin, Y.-H. Wu, and Y.-C. Wu, “High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory,” IEEE Electron Device Letters, vol. 42, no. 9, pp. 1307-1310, 2021.
[5.9] S.-C. Yan, C.-H. Wu, C.-J. Sun, X.-C. Zhong, C.-S. Chang, H.-K. Peng, Y.-H. Wu, and Y.-C. Wu, “Multilevel Cell Ferroelectric HfZrO FinFET With High Speed and Large Memory Window Using AlON Interfacial Layer,” IEEE Electron Device Letters, vol. 44, no. 1, pp. 44-47, 2023.
[5.10] M. H. Park, H. J. Kim, G. Lee, J. Park, Y. H. Lee, Y. J. Kim, T. Moon, K. D. Kim, S. D. Hyun, H. W. Park, H. J. Chang, J.-H. Choi, and C. S. Hwang, “A comprehensive study on the mechanism of ferroelectric phase formation in hafnia-zirconia nanolaminates and superlattices,” Appl. Phys. Rev., vol. 6, no. 4, Dec. 2019, Art. no. 041403, doi: 10.1063/1.5118737.
[5.11] Y. W. Lu, J. Shieh, and F. Y. Tsai, “Induction of ferroelectricity in nanoscale ZrO2/HfO2 bilayer thin films on Pt/Ti/SiO2/Si sub-strates,” Acta Mater., vol. 115, pp. 68–75, Aug. 2016, doi: 10.1016/j.actamat.2016.05.029.
[5.12] S. L. Weeks, A. Pal, V. K. Narasimhan, K. A. Littau, and T. Chiang, “Engineering of ferroelectric HfO2–ZrO2 nanolaminates,” ACS Appl. Mater. Interfaces, vol. 9, no. 15, pp. 13440–13447, Apr. 2017, doi: 10.1021/acsami.7b00776.
[5.13] Y. Peng, W. Xiao, Y. Liu, C. Jin, X. Deng, Y. Zhang, F. Liu, Y. Zheng, Y. Cheng, B. Chen, X. Yu, Y. Hao, and G. Han, “HfO2–ZrO2 superlattice ferroelectric capacitor with improved endurance performance and higher fatigue recovery capability,” IEEE Electron Device Lett., vol. 43, no. 2, pp. 216–219, Feb. 2022, doi: 10.1109/LED.2021.3135961.
[5.14] S. S. Cheema, N. Shanker, L.-C. Wang, C.-H. Hsu, S.-L. Hsu, Y.-H. Liao, M. San Jose, J. Gomez, W. Chakraborty, W. Li, J.-H. Bae, S. K. Volkman, D. Kwon, Y. Rho, G. Pinelli, R. Rastogi, D. Pipitone, C. Stull, M. Cook, B. Tyrrell, V. A. Stoica, Z. Zhang, J. W. Freeland, C. J. Tassone, A. Mehta, G. Saheli, D. Thompson, D. I. Suh, W.-T. Koo, K.-J. Nam, D. J. Jung, W.-B. Song, C.-H. Lin, S. Nam, J. Heo, N. Parihar, C. P. Grigoropoulos, P. Shafer, P. Fay, R. Ramesh, S. Mahapatra, J. Ciston, S. Datta, M. Mohamed, C. Hu, and S. Salahuddin, “Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors,” Nature, vol. 604, no. 7904, pp. 65–71, Apr. 2022, doi: 10.1038/s41586-022-04425-6.
[5.15] S. Migita, H. Ota, S. Asanuma, Y. Morita, and A. Toriumi, “Accelerated ferroelectric phase transformation in HfO2/ZrO2 nanolaminates,” Appl. Phys. Exp., vol. 14, no. 5, May 2021, Art. no. 051006, doi: 10.35848/1882-0786/abfa75.
[6.1] B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, “High performance fully-depleted tri-gate CMOS transistors,” IEEE Electron Device Letters, vol. 24, no. 4, pp. 263-265, 2003, doi: 10.1109/LED.2003.810888.
[6.2] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, and K. Mistry, "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," in Symp. VLSI Technol. Tech. Dig., 2012, pp. 131–132, doi: 10.1109/VLSIT.2012.6242496.
[6.3] W. Yung-Chun, C. Chun-Yen, C. Ting-Chang, L. Po-Tsun, C. Chi-Shen, T. Chun-Hao, Z. Hsiao-Wen, T. Ya-Hsiane, and S. Simon Min, "High performance and high reliability polysilicon thin-film transistors with multiple nanowire channels," in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., 2004, pp. 777–780, doi: 10.1109/IEDM.2004.1419289.
[6.4] Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Jing-Yi Chin, Ping-Hung Yeh, Li-Wei Feng, S. M. Sze, Chun-Yen Chang, Chen-Hsin Lien; Nonvolatile Si/SiO2/SiN/SiO2/Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics. Appl. Phys. Lett. 5 November 2007; 91 (19): 193103. https://doi.org/10.1063/1.2798600.
[6.5] J. Feng, R. Woo, S. Chen, Y. Liu, P. B. Griffin, and J. D. Plummer, “P-channel germanium FinFET based on rapid melt growth,” IEEE Electron Device Lett., vol. 28, no. 7, pp. 637–639, Jul. 2007, doi: 10.1109/LED.2007.899329.
[6.6] B. Liu, X. Gong, G. Han, P. S. Y. Lim, Y. Tong, Q. Zhou, Y. Yang, N. Daval, C. Veytizou, D. Delprat, B. Y. Nguyen, and Y. C. Yeo, “High-Performance Germanium Ω-Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack,” IEEE Electron Device Lett., vol. 33, no. 10, pp. 1336–1338, Oct. 2012, doi: 10.1109/LED.2012.2207368.
[6.7] M. S. Yeh, G. L. Luo, F. J. Hou, P. J. Sung, C. J. Wang, C. J. Su, C. T. Wu, Y. C. Huang, T. C. Hong, T. S. Chao, B. Y. Chen, K. M. Chen, M. Izawa, M. Miura, M. Morimoto, H. Ishimura, Y. J. Lee, W. F. Wu, and W. K. Yeh, "Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment," in Proc. IEEE 2nd Electron Devices Technol. Manuf. Conf. (EDTM), Nov. 2018, pp. 1227–1232, doi: 10.1109/EDTM.2018.8421457.
[6.8] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1930–1936, Nov. 1996, doi: 10.1109/16.543029.
[6.9] J.-W. Lee, N.-I. Lee, H.-J. Chung, and C.-H. Han, “Improved stability of polysilicon thin-film transistors under self-heating and high endurance EEPROM cells for systems-on-panel,” in Int. Electron Devices Meeting (IEDM) Tech. Dig., 1998, pp. 265–268, doi: 10.1109/IEDM.1998.746351.
[6.10] Y.-H. Wu, J.-R.Wu, M.-L.Wu, L.-L. Chen, and C.-C. Lin, “Ge-based nonvolatile memory formed on Si substrate with Ge-stabilized tetragonal ZrO2 as charge trapping layer,” J. Electrochem. Soc., vol. 158, no. 4, p. H410, Oct. 2011, doi: 10.1149/1.3547717.
[6.11] Z.-H. Ye, K.-S. Chang-Liao, L.-J. Liu, J.-W. Cheng, and H.-K. Fang, “Enhanced programming and erasing speeds of charge trapping flash memory device with Ge channel,” IEEE Electron Device Lett., vol. 36, no. 12, pp. 1314–1317, Dec. 2015, doi: 10.1109/LED.2015.2495344.
[6.12] J.-H. Park, D. Kuzum, W.-S. Jung, and K. C. Saraswat, “N-channel germanium MOSFET fabricated below 360◦C by cobalt-induced dopant activation for monolithic three-dimensional-ICs,” IEEE Electron Device Lett., vol. 32, no. 3, pp. 234–236, Mar. 2011, doi: 10.1109/LED.2010.2095827.
[6.13] Q. Xie, S. Deng, M. Schaekers, D. Lin, M. Caymax, A. Delabie, X.-P. Qu, Y.-L. Jiang, D. Deduytsche, and C. Detavernier, “Germanium surface passivation and atomic layer deposition of high-k dielectrics—A tutorial review on Ge-based MOS capacitors,” Semicond. Sci. Technol., vol. 27, no. 7, Jun. 2012, Art. no. 074012, doi: 10.1088/0268-1242/27/7/074012.
[6.14] M. Botzakaki, A. Kerasidou, L. Sygellou, V. Ioannou-Sougleridis, N. Xanthopoulos, S. Kennou, S. Ladas, N. Z. Vouroutzis, T. Speliotis, and D. Skarlatos, “Interfacial Properties of ALD-Deposited Al2O3/p-Type Germanium MOS Structures: Influence of Oxidized Ge Interfacial Layer Dependent on Al2O3 Thickness,” ECS Solid State Lett., vol. 1, no. 2, p. 32, Jul. 2012, doi: 10.1149/2.015202ssl.
[6.15] E. Shigesawa, R. Matsuoka, M. Fukumoto, R. Sano, K. M. Itoh, H. Nohira, and K. Sawano, “Study on Al2O3/Ge interface formed by ALD directly on epitaxial Ge,” Semicond. Sci. Technol., vol. 33, no. 12, Nov. 2018, Art. no. 124020, doi: 10.1088/1361-6641/aaec51.
[6.16] Y.-J. Lee, S.-S. Chuang, F.-K. Hsueh, H.-M. Lin, S.-C. Wu, C.-Y. Wu, and T.-Y. Tseng, “Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 194–196, Feb. 2011, doi: 10.1109/LED.2010.2090937.
[6.17] M. K. Hudait, “Structural and band alignment properties of Al2O3 on epitaxial Ge grown on (100), (110), and (111)A GaAs substrates by molecular beam epitaxy,” J. Appl. Phys., vol. 113, no. 13, Apr. 2013, Art. no. 134311, doi: 10.1063/1.4799367.
[6.18] R. Degraeve, M. Cho, B. Govoreanu, B. Kaczer, M. B. Zahid, J. V. Houdt, M. Jurczak, and G. Groeseneken, "Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks," in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., 2008, pp. 775–778, doi: 10.1109/IEDM.2008.4796812.
[6.19] L. Milani, F. Torricelli, Z. and M. Kovács-Vajna, “Single-poly-EEPROM cell in standard CMOS process for medium-density applications,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3237–3243, Oct. 2015, doi: 10.1109/TED.2015.2461660.
[6.20] J. E. Brewer and M. Gill, Nonvolatile Memory Technologies With Emphasis on Flash, NJ, USA: IEEE Press, 2008, ch. 13, p. 623.
[7.1] Kobayashi, M. A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor. Appl. Phys. Express 2018, 11, 110101.
[7.2] Cheng, K.-L.; Wu, C.C.; Wang, Y.P.; Lin, D.W.; Chu, C.M.; Tamg, Y.Y.; Lu, S.Y.; Yang, S.J.; Hsieh, M.H.; Liu, C.M.; et al. A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell. In Proceedings of the 2007 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 10–12 December 2007; pp. 243–246.
[7.3] Taur, Y.; Ning, T.H. Fundamentals of Modern VLSI Devices, 2nd ed.; Cambridge University Press: Cambridge, NY, USA, 2009.
[7.4] Chandrakasan, A.P.; Brodersen, R.W. Minimizing power consumption in digital CMOS circuits. Proc. IEEE 1995, 83, 498–523.
[7.5] Böscke, T.; Müller, J.; Bräuhaus, D.; Schröder, U.; Böttger, U. Ferroelectricity in hafnium oxide thin films. Appl. Phys. Lett. 2011, 99, 102903.
[7.6] Mueller, S.; Mueller, J.; Singh, A.; Riedel, S.; Sundqvist, J.; Schroeder, U.; Mikolajick, T. Incipient ferroelectricity in Al-doped HfO2 thin films. Adv. Funct. Mater. 2012, 22, 2412–2417.
[7.7] Xu, L.; Nishimura, T.; Shibayama, S.; Yajima, T.; Migita, S.; Toriumi, A. Kinetic pathway of the ferroelectric phase formation in doped HfO2 films. J. Appl. Phys. 2017, 122, 124104.
[7.8] Si, M.; Jiang, C.; Su, C.-J.; Tang, Y.-T.; Yang, L.; Chung, W.; Alam, M.; Ye, P. Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017; pp. 23.5.1–23.5.4.
[7.9] Kwon, D.; Chatterjee, K.; Tan, A.J.; Yadav, A.K.; Zhou, H.; Sachid, A.B.; Reis, R.D.; Hu, C.; Salahuddin, S. Improved subthreshold swing and short channel effect in FDSOI n-channel negative capacitance field effect transistors. IEEE Electron. Device Lett. 2017, 39, 300–303.
[7.10] Lee, M.; Chen, K.-T.; Liao, C.-Y.; Gu, S.-S.; Siang, G.-Y.; Chou, Y.-C.; Chen, H.-Y.; Le, J.; Hong, R.-C.; Wang, Z.-Y. Extremely steep switch of negative-capacitance nanosheet GAA-FETs and FinFETs. In Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 1–5 December 2018; pp. 31.8.1–31.8.4.
[7.11] Tsai, M.-J.; Chen, P.-J.; Hsu, C.-C.; Ruan, D.-B.; Hou, F.-J.; Peng, P.-Y.; Wu, Y.-C. Atomic-level analysis of Sub-5-nm Thick Hf0.5Zr0.5O2 and characterization of nearly hysteresis-free ferroelectric FinFET. IEEE Electron. Device Lett. 2019, 40, 1233–1236.
[7.12] Tsai, M.-J.; Chen, P.-J.; Ruan, D.-B.; Hou, F.-J.; Peng, P.-Y.; Chen, L.-G.; Wu, Y.-C. Investigation of 5-nm-Thick Hf0.5Zr0.5O2 ferroelectric FinFET dimensions for sub-60-mV/decade subthreshold slope. IEEE J. Electron. Devices Soc. 2019, 7, 1033–1037.
[7.13] Liu, C.; Chen, H.-H.; Hsu, C.-C.; Fan, C.-C.; Hsu, H.-H.; Cheng, C.-H. Negative capacitance CMOS field-effect transistors with non-hysteretic steep Sub-60mV/dec swing and defect-passivated multidomain switching. In Proceedings of the 2019 Symposium on VLSI Technology (VLSIT), Kyoto, Japan, 9–14 June 2019; pp. T224–T225.
[7.14] Sun, C.-J.; Yan, S.-C.; Lin, Y.-W.; Tsai, M.-J.; Tsai, Y.-C.; Chou, C.-P.; Hou, F.-J.; Luo, G.-L.; Wu, Y.-C. Comprehensive Study of Inversion and Junctionless Ge Nanowire Ferroelectric HfZrO Gate-All-Around FETs Featuring Steep Subthreshold Slope with Transient Negative Capacitance. ECS J. Solid State Sci. Technol. 2021, 10, 065002.
[7.15] Migita, S.; Morita, Y.; Matsukawa, T.; Masahara, M.; Ota, H. Experimental demonstration of ultrashort-channel (3 nm) junctionless FETs utilizing atomically sharp V-grooves on SOI. IEEE Trans. Nanotechnol. 2014, 13, 208–215.
[7.16] Yeh, M.-S.; Wu, Y.-C.; Wu, M.-H.; Chung, M.-H.; Jhan, Y.-R.; Hung, M.-F. Characterizing the electrical properties of a novel junctionless poly-Si ultrathin-body field-effect transistor using a trench structure. IEEE Electron. Device Lett. 2014, 36, 150–152.
[7.17] Chen, L.-C.; Yeh, M.-S.; Lin, K.-W.; Wu, M.-H.; Wu, Y.-C. Junctionless poly-Si nanowire FET with gated raised S/D. IEEE J. Electron. Devices Soc. 2016, 4, 50–54.
[7.18] Lin, Y.-R.; Cheng, C.-H.; Jhan, Y.-R.; Kurniawan, E.D.; Du, Y.-T.; Lin, Y.-H.; Wu, Y.-C. Hybrid p-channel/n-substrate poly-Si nanosheet junctionless field-effect transistors with trench and gate-all-around structure. IEEE Trans. Nanotechnol. 2018, 17, 1014–1019.
[7.19] Schmidt, M.; Lemme, M.C.; Gottlob, H.; Driussi, F.; Selmi, L.; Kurz, H. Mobility extraction in SOI MOSFETs with sub 1 nm body thickness. Solid-State Electron. 2009, 53, 1246–1251.
[7.20] Toprasertponga, K.; Tahara, K.; Takenaka, M.; Takagi, S. Evaluation of polarization characteristics in metal/ferroelectric/semiconductor capacitors and ferroelectric field-effect transistors. Appl. Phys. Lett. 2020, 116, 242903.
[7.21] Böscke, T.S.; Müller, J.; Bräuhaus, D.; Schröder, U.; Böttger, U. Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors. In Proceedings of the 2011 International Electron Devices Meeting,Washington, DC, USA, 5–7 December 2011; pp. 1–4.
[7.22] Ni, K.; Sharma, P.; Zhang, J.; Jerry, M.; Smith, J.A.; Tapily, K.; Clark, R.; Mahapatra, S.; Datta, S. Critical role of interlayer in Hf0.5Zr0.5O2 ferroelectric FET nonvolatile memory performance. IEEE Trans. Electron. Devices 2018, 65, 2461–2469.
[7.23] Yang, F.-L.; Lee, D.-H.; Chen, H.-Y.; Chang, C.-Y.; Liu, S.-D.; Huang, C.-C.; Chung, T.-X.; Chen, H.-W.; Huang, C.-C.; Liu, Y.-H. 5nm-gate nanowire FinFET. In Proceedings of the 2004 Symposium on VLSI Technology, Honolulu, HI, USA, 15–17 June 2004; pp. 196–197.
[7.24] Yan, S.-C.; Lan, G.-M.; Sun, C.-J.; Chen, Y.-H.; Wu, C.-H.; Peng, H.-K.; Lin, Y.-H.; Wu, Y.-H.; Wu, Y.-C. High speed and large memory window ferroelectric HfZrO2 FinFET for high-density nonvolatile memory. IEEE Electron. Device Lett. 2021, 42, 1307–1310.
[7.25] Yan, S.-C.; Wu, C.-H.; Sun, C.-J.; Zhong, X.-C.; Chang, C.-H.; Peng, H.-K.; Wu, Y.-H.; Wu, Y.-C. Multilevel Cell Ferroelectric HfZrO2 FinFET With High Speed and Large Memory Window Using AlON Interfacial Layer. IEEE Electron. Device Lett. 2023, 44, 44–47.