隨著日益進步的製程技術，為了提升快閃記憶體元件密度以及操作特性，目前廣泛採用高介電常數之堆疊電荷捕捉式記憶體微縮元件或者利用3D堆疊的方式提高單位面積下的元件數量，本論文利用下閘極堆疊方式形成電荷捕捉式快閃記憶體元件，模擬3D製程結構；利用不同材料堆疊形成電荷捕捉層探討其記憶體特性；使用不同的溫度以及堆疊材料形成電荷捕捉層以及穿隧氧化層，尋求低溫製程的最佳製程方式。
第一部分為使用下閘極以及上閘極堆疊利用不同雷射瓦數結晶形成多晶矽電荷捕捉式記憶體元件。實驗結果得知，6.5W樣品沒有元件特性，推測過大的雷射瓦數造成底部金屬的劣化，而在寫入抹除操作特性上，兩種堆疊的特性並無太大的區別。在電荷保持力的部分，下閘極的特性較差，推測是由於活化載子時使氧化層同時退火，造成high-k結晶。
第二部分為使用二氧化鉿、二氧化鋯以及氮化鋯形成電荷捕捉層。由實驗結果得知，二氧化鋯的抹除速度最快，由於二氧化鋯擁有較淺的陷阱深度，在抹除時電子容易跳脫電荷捕捉層。氮化鋯的寫入記憶窗較小但電荷保持力得到提升，推測是由於氮化修復氧化層中的淺缺陷，電子被捕捉在較深的陷阱中。
最後一部分為使用不同溫度以及堆疊材料形成電荷捕捉層以及穿隧氧化層。由實驗結果得知，氮化鋁的寫入抹除速度較快，推測由於高介電常數使穿隧氧化層獲得較大電場。低溫形成的氮化矽寫入記憶窗相比於高溫形成的氮化矽小，推測由於低溫形成的氮化矽氧含量較高，捕捉的電子較少，但在電荷保持力上由於其氧含量較高使能障變大，電子不易流失。最後是元件耐久力的特性，將氧化鋁加在氮化鋯和氮化鋁之間以及高溫沉積的氮化矽表現優異，經過多次的寫入抹除操作後，記憶窗仍保持3V，且臨界偏移較小。

With the advancement of manufacturing technology, in order to improve the device density and operation characteristics, stacking charge trapping flash memory of large permittivity material and using 3D stacked to increase the number of devices per unit area are widely used. This thesis is divided into three parts, the charge trapping flash memory imitate 3D structure formed by bottom gate process; Using different materials to form the charge trapping layer investigate its memory characteristics; Using different temperature and stacked materials to form the charge trapping flash layer and tunneling layer to find the best process method for low temperature processes.
In the first part, using different laser watts formed the polysilicon bottom and top gate stacked charge trapping flash memory. In this work, 6.5W sample show no C-V characteristics, could be attributed to excessive laser watts caused the deterioration of the bottom metal. In terms of programming and erasing operation characteristics, the characteristics of the top and bottom gate device were not much different. Retention of the bottom gate device worse than the top gate device, may be due to the high-k crystallized by annealing when the carrier was activated.
In the second part, the charge trapping layer was formed using hafnium dioxide, zirconium dioxide, or zirconium oxynitride. In this work, the erasing speed of zirconium dioxide was the fastest. Because of the shallower trap level of zirconium dioxide, electrons can easily escape from charge trapping layer during the erasing operation. The program memory window of zirconium oxynitride is smaller but the retention is improved. The nitridation of dielectric may reduce shallow trap in oxide, thus electrons were trapped in deeper trap level.
In the last part, the charge trapping layer and tunneling layer was formed using different temperature and stacked materials. In this work, the programming speed of AlN is the fastest. This could be attributed to the larger permittivity of AlN, the electric field on the tunneling layer is enhanced. On the other hand, the memory window of the low-temperature formed Si3N4 is smaller than the high-temperature formed one. The Si3N4 formed in low temperature has high oxygen content, electrons captured in charge trapping layer is reduced. However, the retention of Si3N4 formed in lower temperature is better. The energy barrier gets larger because of the high oxygen content. As a result, the electron trapped in trapping layer is hard to escape. In terms of the endurance, depositing Si3N4 in high temperature or inserting Al2O3 between the ZrON and AlN show less threshold voltage shift after 10,000 program/erase cycles.

摘要 i
ABSTRACT ii
致謝 iv
目錄 v
圖目錄 viii
表目錄 xi
第1章 序論 1
1.1. 快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體 1
1.1.2 電荷捕捉式快閃記憶體 2
1.2. 多晶矽薄膜電晶體 3
1.3. 多向式閘極結構與奈米線通道式快閃記憶體元件 4
1.3.1 多向式閘極結構 4
1.3.2 三維結構與奈米線結構與環繞閘極結構 4
1.4.高介電係數材料與能帶工程 5
1.4.1高介電係數材料 5
1.4.2能帶工程 6
1.4.3高介電係數之材料應用在阻擋氧化層 7
1.5無接面快閃記憶體元件 7
1.6各章摘要 10
第2章 快閃記憶體元件製作與操作方式 17
2.1. 快閃記憶體元件製造 17
2.1.1 三閘極式無接面快閃記憶體元件製作 17
2.1.2 下閘極堆疊電容式記憶體元件製作 18
2.2. 無接面電荷捕捉式快閃記憶體寫入與抹除 18
2.2.1 通道熱電子注入寫入(Channel Hot Electron injection, CHEI) 18
2.2.2 FN穿隧寫入與抹除 19
2.2.3 直接穿隧 20
2.3. 電荷捕捉式快閃記憶體元件可靠度分析 21
2.3.1 元件耐久力 21
2.3.2 電荷保持力(Retention) 22
2.4. 閘極與汲極之干擾特性 23
第3章 利用雷射退火形成多晶矽下閘極堆疊電荷捕捉式記憶體 35
3.1. 研究動機與背景 36
3.2. 實驗流程 36
3.2.1 元件之遲滯特性圖 38
3.2.2 元件寫入與抹除特性 39
3.2.3 元件可靠度特性 39
3.3. 結論 40
第4章 利用不同材料的堆疊式電荷捕捉氧化層比較多晶矽快閃記憶體之特性 50
4.1. 研究動機與背景 51
4.2. 實驗流程 51
4.3. 結果與討論 52
4.3.1 元件之汲極電流對閘極電壓特性圖 52
4.3.2 元件寫入與抹除特性 53
4.3.3 元件可靠度特性 54
4.4. 結論 54
第5章 在低溫環境下堆疊電荷捕捉層以提升多晶矽無接面快閃記憶體元件之特性 62
5.1. 研究動機與背景 62
5.2. 實驗流程 63
5.3. 結果與討論 65
5.3.1 元件之汲極電流對閘極電壓特性作圖 65
5.3.2 元件的寫入與抹除特性 65
5.3.3 元件可靠度特性 66
5.4. 結論 67
第6章 總結 76
6.1. 結論 76
6.2. 未來展望 77

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