近年來，隨著製程技術不斷的進步，元件特徵尺寸微縮，透過不同結構或通道材料來改善電特性，可以克服短通道效應所造成的問題。隨著元件微縮，以往舊有的二氧化矽作為閘極氧化層已不堪再使用，因為閘極漏電變的嚴重，因此使用高介電材料比如二氧化鉿來做取代，雖然高介電材料可以減低閘極漏電流，但也會導致載子遷移率的下降，因此提出矽鍺材料作為虛擬基板來解決此問題。矽鍺為可提升元件導通電流的材料，因為鍺材料比起矽有著較高的載子遷移率，在電子與電洞分別為兩倍與四倍的提升，另外在矽和鍺之間有著4.2%的晶格常數不匹配，因而產生壓縮或是拉伸的應變來提升載子遷移率。
第一部分，取代傳統鰭式電晶體中的矽材料，以矽與矽鍺交互堆疊的矽鍺超晶格為通道材料，提升載子遷移率。從實驗結果來看，不論是N通道之鰭式電晶體還是全環繞式閘極電晶體，Si/SiGe一個循環(1P)比起Si/SiGe兩個循環(2P)在導通電流、關閉電流、次臨界擺幅，都有較好的表現。推測隨著矽鍺堆疊的層數越多，且通道兩側並無矽帽去抑制鍺的擴散，對於鍺擴散到閘極介面的機率會越高，產生之缺陷也會隨之變多。而與Si n-GAAFET相比，Si/SiGe 1P n-GAAFET由於矽與矽鍺間產生的拉應力，產生較好的導通電流，雖然矽帽對於抑制鍺擴散有著一定的作用，然而在關閉電流、On/Off ratio、次臨界擺幅還是有劣化的趨勢，主要是因為在通道的兩側並無矽帽去抑制鍺的擴散，但是劣化的並不多，若對介面加以處理，更能凸顯矽鍺超晶格通道的優點。
第二部分與第一部分相同的基板條件，但應用在P通道中。理論上鍺的電洞遷移率比起矽有著大約四倍的提升，且矽與矽鍺之間會產生應力去提升導通電流，但矽鍺超晶格通道之元件，其導通電流並無太大之提升，除了與第一部分有著相同的缺陷之外，推測還存在著較低遷移率的電洞在矽通道中傳導。
最後為綜合兩個章節實驗的可靠度，可以看到不論是N通道還是P通道，在通道存在著越多的鍺含量，其臨界電壓以及最大轉導值的衰退會越嚴重，是由於越多鍺含量的通道，其介面缺陷越多，而特性上也會更加劣化。而在不同閘極結構的部分來看，發現四面環繞比起三面環繞之閘極結構，其臨界電壓衰退的較少，是由於靜電閘控能力的提升，不過在最大轉導值衰退的部分來看，兩者差異不大，推測最大轉導值的衰退與閘控能力的提升並無太大關連。

In recent years, the feature sizes of MOSFET device were reduced with the continuous advancement of manufacturing process technology, by which the short channel effects can be overcome. The electrical characteristics of MOSFET can be improved through different device structures or channel materials. With the shrinking of device, the traditional silicon dioxide can not be further used as gate dielectric, because the gate leakage becomes serious. A high-k dielectric such as hafnium dioxide is applied to replace silicon dioxide. Although a high-k gate dielectric can suppress the gate leakage, it may also cause a decrease in carrier mobility. So, a SiGe virtual substrate was proposed to resolve this problem. The on-current of device can be increased with a SiGe channel. Ge has higher carrier mobility than silicon, with twice and four times the increase in electrons and holes, respectively. A 4.2 % mismatch of lattice constant between Si and Ge would result in compressive or tensile strain to increase carrier mobility.
In the first part, the electron mobility of n-channel FET is enhanced by using Si/SiGe super-lattice (SL) channel with strain effects. Experimental results show that the on/off current and sub-threshold swing (S.S.) of both n-FinFET and n-GAAFET with Si/SiGe SL of one period (1P) are better than those with Si/SiGe SL of two periods (2P). More defects are generated with more stacked SiGe layers, which may be because both sidewalls of the channel without Si-cap cannot suppress Ge diffusion from channel to gate oxide. Compared with Si n-GAAFET, the on current of 1P Si/SiGe SL one is higher due to the tensile stress between Si and SiGe. Although Ge diffusion is suppressed with a Si-cap, the off current, on/off current ratio, and S.S. are slightly degraded, possibly because there are no Si-caps on both sidewalls of the channel to suppress the Ge diffusion. If the interface can be passivated, the advantages of the SiGe SL channel shall be clearer.
The p-FinFET and p-GAAFET with the same channel structures as the first part were also investigated. Although the hole mobility of Ge is much higher than Si and the strain effects in Si/SiGe SL channel may enhance the on current, the on current of devices with SiGe SL channel are not clearly improved. The little improvement may be attributed to the similar effects of Ge diffusion on the sidewalls of channel, and the on current may be reduced by the lower mobility of hole conduction in the Si channel.
Finally, the reliability characteristics for both n- and p-FET were comprehensively studied and compared. It can be seen that the stress-induced threshold voltage(Vth) shift and maximum transconductance (Gmmax) degradation are more for both n-and p-FET with more Ge contents in the channel, which could be attributed to the more defects induced by more Ge diffusion. Regarding to the effects of channel structure, it is found that the stress-induced Vth shift in GAAFET is smaller than that in FinFET, probably due to the better gate control ability of the former device. However, the stress-induced Gmmax degradation in GAAFET is similar to that in FinFET, possibly because Gmmax is less sensitive to gate control ability.

摘要 i
Abrstract iii
致謝 iii
目錄 vi
圖目錄 ix
表目錄 xiii
第一章 序論 1
1.1 前言 1
1.2 高介電材料(High-k)介紹 1
1.3 高介電材料的選擇 2
1.4 矽鍺薄膜製作 3
1.5 應變矽技術 3
1.6 矽鍺虛擬基板-應變通道 4
1.6.1 臨界厚度 5
1.6.2 差排 5
1.7 鰭式電晶體(FinFET)、全環繞式閘極電晶體(GAAFET) 6
1.8 論文架構 6
第二章 元件製程與量測 19
2.1 SOI 電晶體製作流程 19
2.1.1 晶圓刻號與清潔 19
2.1.2 晶圓對準記號形成 19
2.1.3 主動區形成 20
2.1.4 閘極介電層沉積 20
2.1.5 金屬閘電極的形成 20
2.1.6 源極(Source)、汲極(Drain)、基極(Base)的形成 20
2.1.7 鈍化層沉積 20
2.1.8 金屬導線、燒結 21
2.2 電性的量測 21
2.2.1 電晶體電流-電壓(I-V)特性量測 21
2.3 物性分析 22
2.3.1 穿透式電子顯微鏡 22
第三章 矽鍺超晶格通道於N型鰭式電晶體、全環繞式電晶體之電性及可靠度分析 26
3.1 研究動機 27
3.2 製程與量測 28
3.2.1 製程流程條件 28
3.2.2 量測參數 28
3.3 實驗結果與討論 29
3.3.1 矽鍺超晶格通道鰭式電晶體、全環繞式電晶體在穿透式電子顯微鏡下的分析 29
3.3.2 矽鍺超晶格N通道鰭式電晶體之電特性分析 30
3.3.3 矽、矽鍺超晶格N通道全環繞式電晶體之電特性分析 32
3.3.4 鰭式與全環繞式閘極N通道電晶體之電性及可靠度分析 35
3.4 本章結論 35
第四章 矽、矽鍺超晶格通道於P型鰭式電晶體、全環繞式閘極電晶體之電性及可靠度分析 56
4.1 研究動機 56
4.2 製程與量測 57
4.2.1 製程流程條件 57
4.2.2 量測參數 58
4.3 實驗結果與討論 58
4.3.1 矽鍺超晶格通道鰭式電晶體、全環繞式電晶體在穿透式電子顯微鏡下的分析 58
4.3.2 矽鍺超晶格P通道鰭式電晶體之電特性分析 58
4.3.3 矽、矽鍺超晶格P通道全環繞式電晶體之電特性分析 60
4.3.4 鰭式與全環繞式閘極P通道電晶體之電性及可靠度分析 63
4.4 本章結論 64
第五章 結論與未來展望 82
5.1 結論 82
5.2 未來展望 83
參考文獻 84

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