隨著元件特徵尺寸微縮，氧化層過薄導致關閉電流急遽增加，閘極堆疊與氧化層對元件之可靠度開始受到重視，本論文研究之重點為閘極堆疊介面處理對電容及鰭式電晶體閘極漏電流與介電層可靠度之影響。在Gate-late process中利用電漿對偽閘極(dummy gate)進行蝕刻時會對通道表面造成損害，透過氫退火處理可以有效修復表面缺陷並使表面更平滑；高介電常數氧化層熱穩定性差，在退火後容易結晶導致閘極漏電流遽增，將介電層氮化可以提升結晶溫度並鈍化氧空缺，改善其熱穩定性；氧化鑭本身具有強烈的吸濕性，容易導致電性劣化與介電層粗糙度增加等問題，必須藉由退火並臨場沉積阻擋層克服吸水的問題。
第一部份，在矽表面蝕刻並進行不同溫度與濃度之氫氣退火並製成電容元件。經過退火後的元件閘極漏電流都能被抑制，電容值、氧化層厚度及平帶電壓則幾乎不改變。在氫濃度較高的環境中退火能在抑制閘極漏電流的同時元件可靠度不下降，經AFM分析後發現其表面粗糙度降低，推測可靠度與表面粗糙度相關。
第二部分，在取代式金屬閘極製程中，蝕刻dummy gate後的矽通道表面進行不同溫度與濃度之氫氣退火並製成N型與P型鰭式電晶體元件。將退火溫度提高時能降低關閉電流，閘極漏電流也因而下降，推測退火溫度提高時表面遷移的現象較明顯，因而改善電性；其他特性如次臨界擺幅、轉導、臨界電壓特性則不受退火環境影響。純氫氣退火之樣本在N型電晶體特性上有劣化的趨勢，可能由於其低溫限制，表面修復之效果不足而導致。
第三部分，利用離子佈植加上退火將介電層氮化並製成N型與P型鰭式電晶體。介電層經過氮化後的元件閘極漏電流大幅下降，在經過F-N stress後臨界電壓偏移的情況也能夠降低，推測氮化後介電層的結晶減少且氧空缺被鈍化，使漏電路徑與陷阱輔助之穿隧電流減少，而氧化層中之陷阱量降低，元件可靠度也因而改善。
第四部份，在閘極介電層沉積後以不同氣體與時間退火並臨場沉積阻擋層，製成N型與P型鰭式電晶體。經過退火後的電晶體，關閉電流與閘極漏電流幾乎都有下降的趨勢，惟氫氣退火之樣本關閉電流增加，可能因退火時氫氣滲透至源汲極導致摻雜擴散；在氨氣環境下退火時閘極漏電流改善的情形最為明顯，推測是氨氣對介電層有氮化的效果；而退火時間較長的樣本在經過stress後臨界電壓偏移的情形有惡化的趨勢，可能是氧化層缺陷在退火時增加，因此必須謹慎控制熱預算避免元件劣化。

As the feature size of MOSFET shrinks, the ultrathin gate oxide has caused a dramatic increase in the leakage current. As a result, the reliability issue of gate stacks and dielectric layers becomes a growing concern. The effects of gate-stack interfacial treatments on the gate leakage current and the dielectric reliability of MOS capacitors and FinFETs are investigated. In gate-last process, the dummy gate is removed by a plasma process, which often induces etching damage on channel surface. It was reported that an annealing in hydrogen ambient on Si channel is useful to remove defect and smoothen surface. In addition, the thermal stability of high-k dielectric is a generally concern. The crystallization of high-k dielectric, which causes drastic increase in gate leakage current, is usually observed after an annealing. It has been found that the nitridation of high-k dielectric can raise the crystallization temperature and passivate the oxygen vacancy, thus the thermal stability can be improved. Moreover, the moisture absorption of lanthanum oxide has been an issue, which may result in electrical degradation and increased roughness of gate dielectric. To overcome the hygroscopic issue, the annealing treatments in suitable ambient on high-k gate dielectric and in-situ deposition of barrier layer may be feasible solutions.
In the first part, hydrogen annealing at different temperatures and hydrogen/nitrogen ratios on the surface-etched silicon were applied on MOS capacitors. Suppressed gate leakage current can be observed in all samples with hydrogen annealing, while the capacitance, the EOT, and the flat-band voltage are not changed. The AFM image shows that the surface roughness can be reduced by annealing at higher hydrogen ratio, which achieves lower gate leakage current without degradation on reliability.
In the second part, during replacement metal gate process, hydrogen annealing at several temperatures and hydrogen/nitrogen ratios on the silicon-channel surface were performed after dummy gate etching in N-type and P-type FinFETs. The off-state current and the gate leakage current can be reduced by raising the annealing temperature, which may be due to the enhancement of the surface migration effect. On the other hand, the subthreshold swing, the transconductance, and the threshold voltage are not influenced by different annealing conditions. The gate leakage current and stress-induced threshold voltage shift are increased by annealing in pure hydrogen ambient in N-type FinFET. The degradation can be attributed to the low-temperature limitation, with the insufficient effect of surface passivation.
In the third part, incorporating nitrogen into the gate dielectric through ion implantation and succeeding annealing were applied on N-type and P-type FinFETs. Sample with nitrogen incorporation exhibits significant decrease in the gate leakage current and lower stress-induced threshold voltage shift. The nitridation of dielectric may suppress the crystallization of dielectric and passivate the oxygen vacancy, thus the leakage path and the trap-assist tunneling current can be diminished. The reliability can also be improved due to the less oxide trap.
In the fourth part, N-type and P-type FinFETs were annealed at various gas ambient and different durations after gate dielectric deposition, followed by in-situ barrier layer deposition. Except for those annealed in hydrogen ambient, devices annealed in other ambient demonstrate lower off-state current and gate leakage current. Sample annealed in hydrogen ambient show increased off-state current, which may be caused by the penetration of hydrogen into source/drain and result in out-diffusion of dopants. Devices with NH3 annealing show the lowest gate leakage current among all. This improvement can be attributed to the nitridation of the dielectric. The degradation on the stress-induced threshold voltage shift can be observed in samples with long-time annealing, suggesting that the oxide trap is increased in annealing process. As a result, the thermal budget of post-deposition annealing should be carefully controlled to avoid device degradation.

摘要 i
Abstract iii
致謝 v
目錄 vi
表目錄 ix
圖目錄 x
第一章 序論 1
1.1 前言 1
1.2 電晶體尺寸微縮 1
1.3 鰭式場效電晶體 1
1.4 氧化層微縮及其產生之影響 2
1.5 電漿產生之表面損傷 2
1.6 矽表面高溫氫退火 3
1.7 高介電常數氧化層之氮化效應 3
1.8 氧化鑭沉積後退火 4
1.9 論文架構 5
第二章 元件製程與量測 19
2.1 電容標準製程 19
2.2 電容電性量測 19
2.2.1 基礎電性量測 20
2.2.2 可靠度量測 20
2.3 鰭式電晶體製造流程 20
2.4 電晶體電性量測 21
2.4.1 基礎電性量測 21
2.4.2 可靠度量測 22
第三章 矽表面氫退火處理之電容特性研究 25
3.1 研究動機 25
3.2 製程與量測 26
3.3 結果與討論 27
3.4 結論 28
第四章 矽表面氫退火處理之電晶體特性研究 38
4.1 研究動機 38
4.2 製程與量測 39
4.2.1 製程條件 39
4.2.2 量測參數 39
4.3 結果與討論 39
4.4 結論 41
第五章 以離子佈植氮化high-k層之電晶體特性研究 52
5.1 研究動機 52
5.2 製程與量測 53
5.2.1 製程條件 53
5.2.2 量測參數 53
5.3 結果與討論 54
5.4 結論 55
第六章 氧化鑭沉積後退火之電晶體特性研究 65
6.1 研究動機 65
6.2 製程與量測 66
6.2.1 製程條件 66
6.2.2 量測參數 66
6.3 結果與討論 67
6.4 結論 69
第七章 結論與未來展望 79
7.1 結論 79
7.2 未來展望 80
參考文獻 81

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