近年消費性電子產品的市場需求，持續推動著CMOS製程技術的演進，然而為了同時滿足高運算速度、高效能、低功耗與低成本等需求，單純於結構上進行微縮，例如縮短通道長度與降低閘極氧化層厚度，已逐漸無法達成如此艱巨的任務。近年來鐵電負電容電晶體因其可同時提高驅動電流並降低能耗的特點，成為許多研究的焦點，且藉由高載子遷移率通道材料，例如矽鍺、鍺等，還可更進一步提升效能。此外於元件微縮方面，將NMOS與PMOS垂直堆疊於同一平面的互補式場效電晶體(Complementary FET, CFET)，可以大大提升電晶體密度，相關的研究也逐漸備受關注。因此本論文旨在應用於莫爾定律之延伸，探討高遷移率通道材料之鐵電負電容電晶體與高遷移率通道材料於互補式場效電晶體之應用。本論文共分為三個部份，(1) 鍺通道反轉式與無接面式鐵電負電容環繞閘極場效電晶體，(2) 高高寬比矽鍺通道鰭式場效電晶體與自發性鍺摻雜之倒T形矽鍺∕矽雙層通道鐵電負電容環繞式閘極場效電晶體，(3)以矽鍺通道鍺比例調變互補式場效電晶體臨界電壓之研究。
第一部分以高載子遷移率鍺作為通道材料，分別製作出傳統反轉式與無接面式氧化鉿鋯鐵電負電容繞式閘極場效電晶體，透過分析無接面式電晶體的電流傳導機制，開關切換過程與傳統反轉式電晶體相似，受到半導體表面電位影響，提出鐵電負電容效應亦可應用於無接面式電晶體上，亦可因其使表面電位放大，而獲得較低的SS。
第二部分提出，以等向性蝕刻開發高高寬比矽鍺通道鰭式電晶體，接著利用相同製程概念，製作出倒T形矽鍺∕矽雙層通道環繞式閘極場效電晶體，並且同時探討其由矽鍺通道自發性將鍺摻入氧化鉿閘極氧化層中的鐵電負電容特性。於高高寬比矽鍺通道鰭式電晶體的研究中，藉由矽鍺通道的高載子遷移率與高高寬比鰭式結構所帶來的閘極控制能力，可同時提高驅動電流及降低關電流。倒T形矽鍺∕矽雙層通道環繞式閘極鐵電場效電晶體的研究中，驗證了矽鍺通道自發性將鍺摻入氧化鉿，退火結晶形成鐵電氧化層，並且結合倒T形環繞式閘極的結構，達到了平均次臨界擺幅(SS)低於60mV/decade。
第三部份我們利用Sentaurus TCAD針對三維堆疊單晶片(monolithic) CFET進行探討。未來高度微縮的CFET元件，於水平方向與垂直方向的堆疊空間，將分別被閘極長度與垂直通道間隙所限制，進而導致雙功函數金屬(dual work function metal)製程的困難，因此在此部分研究中，我們提出利用控制矽鍺通道的鍺含量來調整CFET臨界電壓(VT)，這是一項零體積(volume-less)的調整VT方法。我們首先分別分析了矽鍺通道中鍺含量的變化，對NMOS與PMOS的影響，並提供了以此方式調整VT的細節步驟，最後展示出設計的CFET反向器(inverter)特性，以及以此反向器為基礎架構出的6T-SRAM。

In recent years, the market demand for consumer electronic products has been driving the evolution of CMOS process technology. However, merely scaling down device structures, such as shortening channel lengths and reducing gate oxide thickness, is gradually proving inadequate to meet the challenging requirements of high computational speed, efficiency, low-power consumption, and cost-effectiveness. As a result, researchers are focusing on novel approaches, such as ferroelectric negative capacitance FET (NCFET) for lowering power consumption, involving high-mobility channel materials for enhance operation speed, and exploring the potential of Complementary FET (CFET) to significantly improve transistor density. This thesis is divided into three parts.
Part 1 investigates Ge channel NCFET, both conventional inversion-mode and junctionless (JL) structures with hafnium zirconium oxide ferroelectric negative capacitance. The study proposes that since the junctionless FET operates similarly to the conventional inversion-mode one, influenced by the semiconductor surface potential, the NC effect can also be applied to the JLFET, leading to a lower subthreshold swing (SS) due to enhanced surface potential.
Part 2 introduces a novel approach to fabricating high-aspect-ratio SiGe channel FinFETs through isotropic etching. Additionally, it explores the characteristics of an Inverted-T gate-all-around FET (IT-GAAFET) with a SiGe/Si double-channel structure, where germanium is spontaneously doped into the hafnium oxide gate oxide to achieve ferroelectric negative capacitance. The research on high-aspect-ratio SiGe channel FinFETs indicates that leveraging the high carrier mobility and gate control ability of SiGe channels can enhance drive current and reduce off-state leakage current at the same time. Meanwhile, the IT-GAAFET with the dual-channel structure successfully achieves an average subthreshold swing below 60 mV/decade.
Part 3 focuses on the three-dimensional stacked monolithic CFET using Sentaurus TCAD simulations. As device scaling continues, the stacking space in both horizontal and vertical directions will be limited by gate length and vertical channel pitches, making dual-work function metal processing challenging. To address this, a zero-volume adjustment method for the CFET threshold voltage (VT) is proposed, based on controlling the germanium content in the SiGe channel. The study analyzes the impact of varying germanium content on NMOS and PMOS and provides detailed steps for VT tuning. Finally, the design of a CFET inverter and a 6T-SRAM cell based on this inverter are presented.

中 文 摘 要 i
Abstract iii
Acknowledgement vi
Contents vii
List of Figures x
List of Tables xvii
Chapter 1 Introduction 1
1-1 Challenges of Device Scaling and Opportunities 1
1-2 Scaling for Transistor Architecture 5
1-2.1 Multi-Gate Field-Effect Transistor 6
1-2.2 Complementary Field-Effect Transistor 9
1-3 High mobility channel materials 10
1-4 Junctionless Field-Effect Transistor 12
1-5 Organization of the research 16
1-6 Reference 18
Chapter 2 Ferroelectric Negative Capacitance Theory 23
2-1 Boltzmann limit and Negative Capacitance (NC) FET 23
2-2 What is negative capacitance? 28
2-3 Ferroelectric negative capacitance and Landau theory 30
2-4 Experimental observation of negative capacitance and S-curve 34
2-5 Experimental steep slope NCFETs 37
2-6 Interpretation of the physic of NC in NCFETs 39
2-7 Negative Drain-induced barrier lowering (N-DIBL) 44
2-8 Reference 46
Chapter 3 Comprehensive Study of Inversion and Junctionless Ge Nanowire Ferroelectric HfZrO Gate-all-around FETs featuring Steep Subthreshold Slope with Transient Negative Capacitance 53
3-1 Motivation and Literature Review 53
3-2 Device Fabrication 56
3-3 Results and Discussion 58
A. Characteristic of inversion mode n-type and p-type Ge FE-GAAFET 58
B. Ferroelectric TNC effect apply on Ge junctionless NW-GAAFET 65
3-4 Summary 70
3-5 References 71
Chapter 4 SiGe Ultra-thin FinFET and Negative Capacitance SiGe/Si Bilayer Inverted-T Channel GAAFET 77
4-1 Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-type FinFET with Low Off State Leakage and High ION/IOFF ratio 77
4-1.1 Motivation and Literature Review 77
4-1.2 Device Fabrication 78
4-1.3 Results and Discussion 80
4-1.4 TCAD simulation 88
4-1.5 summary 89
4-2 Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-all-around Field-effect-transistor with Self-induced Ferroelectric Ge doped HfO2 90
4-2.2 Device Fabrication 91
4-2.3 Results and Discussion 94
4-2.4 TCAD simulation 101
4-2.5 Summary 102
4-3 Reference 104
Chapter 5 Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET) 116
5-1　Motivation and Literature Review 116
5-2　Device Structure and Simulation Approach 118
5-3　Results and Discussion 121
5-4　Summary 130
5-5　Reference 132
Chapter 6 Conclusion 138
Curriculum Vitae 140
Publication List 141
Appendix 145

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