隨著近年來半導體的發展，鍺材料被視為有機會取代矽做為元件通道的來料之一。但是仍然有需多待被克服的問題。例如:鍺缺乏穩定的熱氧化物導致其介面品質較差。因此需藉由介面工程改善這些應用上的問題，優化其介面品質。本論文利用氫處裡優化介面品質，文獻指出使用適當的氫處裡可以有效的降低氧化層之缺陷以及降低EOT，希望藉由氫處裡得到又薄、結構又緻密的GeO2作為氧化層。此外也探討Al2O3以及HfNx介面層改善，根據文獻指出使用 HfNx作為NMOS之介面層可以有效鈍化介面，而利用Al2O¬3薄膜作為擴散控制層（DCL）。此外，實驗中也成功做出全閘極環繞式電晶體提升電特性，並抑制短通道效應。
第一部分是進行n-FinFET與的討論，實驗首先使用氫處裡過後的介面層做研究，實驗中也引入兩種不同材料HfNx、Al2O¬3作為介面層。使用熱穩定性較高之Al2O3做為保護層，抑制製程中所形成介面的損傷，另外可以有效鈍化表面的HfNx介面層，分別比較ZrO2/Al2O3/H2/GeO2、ZrO2/HfNx/H2/GeO2、ZrO2/HfNx/RTO/GeO2之特性。從實驗結果來看，透過氫處裡後的樣品，對於導通電流以及S.S.都有較好的表現。此外應用HfNx作為介面層的元件有良好的驅動電流表現，且使用氫處裡搭配HfNx之S.S.特性也是所有樣品中最小的。
實驗第二部份則是延續的一部份的介面處裡，並應用在p-FinFET與p-GAAFET上，實驗中發現ZrO2/Al2O3/H2/GeO2之樣品有較好抑制漏電流的效果，並在On/Off ratio優於ZrO2/HfNx/H2/RTO之樣品，可靠度方面也有較佳的表現。由此可知而在p型態鍺電晶體使用ZrO2/Al2O3/H2/GeO2作為介面層對於元件的穩定性較佳且元件開關電流也有較優異的表現。

With the development of semiconductors in recent years, germanium is regarded as one of the potential materials to replace silicon for the device channel. However, several problems should be resolved. For example, the unstable Ge oxide leads to poor interface quality. Therefore, interface engineering is needed to improve these problems and optimize the interface quality. A hydrogen plasma treatment was used to optimize the interface quality. It was reported from literatures that oxide defects and EOT can be effectively reduced by a suitable hydrogen plasma treatment. A thin, dense and structured GeO2 may be obtained as an interfacial layer by a hydrogen plasma treatment. In addition, effects of Al2O3 and HfNx interface layer were also studied. It was reported from literatures that the interface of n-channel MOSFET can be effectively passivated by a HfNx interfacial layer , and Al2O3 film is good for the diffusion control layer . In addition, improved electrical characteristics and suppressed short-channel effects are achieved by forming a gate-all-around channel structure for FET in this thesis.
n-FinFET was studied in the first part. The interface layer was formed with a hydrogen plasma treatment. HfNx and Al2O3 were studied for the interface layer. The thermally stable Al2O3 is a good diffusion barrier to suppress the interface trap generation during the process. In addition, the HfNx interface layer is useful to passivate the Ge surface. Hence, electrical characteristics of n-FinFETs with ZrO2/Al2O3/H2/GeO2, ZrO2/HfNx/H2/GeO2, ZrO2/HfNx/RTO/GeO2 gate stacks were studied and compared. From the experimental results, the samples with hydrogen plasma treatments have better performance. In terms of on-current and subthreshold swing (S.S.). In addition, sample with HfNx interface layer has the highest on-current, and the S.S. values of devices with hydrogen plasma treatment and HfNx interfacial layer are the smallest among all samples.
The hydrogen plasma treatment, HfNx and Al2O3 interfacial layers were also studied for p-FinFET and p-GAAFET. It is found that the off-current of Ge pFinFET is suppressed with a ZrO2/Al2O3/H2/GeO2 gate sack. And the characteristics of On/Off ratio and reliability are improved with a ZrO2/HfNx/H2/RTO gate stack. Therefore, a higher on/off current ratio and better reliability in Ge p-channel FET can be obtained with a ZrO2/Al2O3/H2/GeO2 gate stack.

摘要 I
ABSTRACT II
致謝 IV
目錄 V
圖目錄 VIII
表目錄 XI
第一章 序論 1
1.1 前言 1
1.2 使用純鍺基板作為載子通道材料 1
1.3 高介電係數(HIGH-K)材料作為閘極氧化層 2
1.4 高介電係數(HIGH-K)材料的選擇 2
1.5 介面層的形成方式 3
1.6 介面缺陷鈍化 4
1.7 氮化鉿作為P型鍺基板之閘極介面層 5
1.8 絕緣層覆矽基板 5
1.9 鰭式電晶體(FINFET)、全環繞式電晶體(GAAFET) 5
1.10 論文架構 6
第二章 元件製程與量測 20
2.1 SOI 電晶體製作流程 20
2.1.1 晶圓刻號與清潔 20
2.1.2 晶圓對準記號形成 20
2.1.3 主動區形成 20
2.1.4 閘極介電層沉積 21
2.1.5 金屬閘電極的形成 21
2.1.6 源極(Source)、汲極(Drain)、基極(Base)的形成 21
2.1.7 鈍化層沉積 21
2.1.8 金屬導線、燒結 22
2.2 電性的量測–電晶體電流-電壓(I-V)特性量測 22
2.3 物性分析–穿透式電子顯微鏡 22
第三章 不同介面層對N型鍺鰭式電晶體電性分析 28
3.1 研究動機 28
3.2 製程與量測 30
3.2.1製程流程條件 30
3.2.2量測參數 30
3.3 結果與分析 31
3.3.1 N型鍺FinFET電性分析 31
3.4 可靠度與均勻度分析 32
3.5 本章結論 33
第四章 不同介面層對P型鍺鰭式電晶體與全閘極環繞式電晶體電性分析 41
4.1 研究動機 41
4.2 製程與量測 42
4.2.1製程流程條件 42
4.2.2量測參數 43
4.3 結果與分析 43
4.3.1鰭式、全環繞式電晶體之條件 43
4.3.2 P型鍺FinFET與GAAFET電性結果 43
4.4 可靠度與均勻度分析 46
4.5 本章結論 47
第五章 結論與未來展望 62
5.1 結論 62
參考文獻 64

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