隨著科技的進步，電子產品與我們生活有著很密切的結合，對於這些電子產品的要求也逐漸往高效能、低功耗以及小尺寸，其中降低功耗會是目前較為重要的項目，而現在半導體的尺寸也要到了極限，短通道效應會是相當嚴重的問題，要持續地增進半導體產業的發展，在未來開發其他材料或是改變結構便是持續發展的一個方向，相較於現今所使用的矽，鍺是個擁有高電子與電洞遷移率，因此這項材料有機會成為取代矽的新材料。
在本篇論文運用了絕緣層覆矽基板，並在上面製作出鍺通道無接面式場效電晶體，同時將閘極氧化層轉換成具有鐵電效應的材料，使該電晶體達到更好的功率，同時因應現今產業的發展，使這些技術能結合到未來小尺寸的電晶體上。本篇論文成功的製作出P型環繞式鍺通道奈米線的無接面式鐵電電晶體以及對照組，證實了鐵電效應可以在無接面式電晶體上應用，鐵電效應可以使次臨界斜率(subthreshold swing)低於物理極限和汲極引致能障下降(Drain-induce Barrier Lowing)程度變低，當元件的微縮時可以發現此元件對短通道效應是不敏感的。最後一部分藉由Sentaurus TCAD模擬軟體和數值分析對電晶體與電容的特性進行探討，其中包含了兩個不同物理的模組，而這兩個模組個別說明了鐵電效應為準靜態或是暫態，最後的研究分別對實驗數據進行比較，並證明了這兩個模組的正確性。
此鍺通道奈米線之無接面式鐵電場效電晶體有著簡單的製程，並能得到良好的特性，因此在未來低功耗、高效能元件的發展是非常有潛力的。

With the advancement of science and technology, electronic products have been closely integrated with our lives. The requirements for these electronic products are gradually moving towards high performance, low power consumption and small size. Among them, low power consumption will be a more important project at present. The size of the field-effect-transistor has also reached its limit. The short channel effect is a very serious problem under continuous scaling. To improve the problem, the development of other materials or changing the structure in the future is a direction of continuous development. Compared to silicon, germanium has high electron and hole mobility, so it has the opportunity to become a new material to replace silicon.
In this thesis, germanium channel junctionless field-effect-transistor is fabricated on Silicon on Insulator (SOI) wafer. At the same time, the gate oxide is converted into a material with ferroelectric effect, so that the device can achieve better performance. While responding to the development of the industry, these technologies enable combine with future small-sized transistors. The thesis successfully produced p-type gate-all-around germanium channel nanowire junctionless ferroelectric field-effect-transistor and the control group. It is proved that the ferroelectric effect can be applied to the junctionless transistor and make the subthreshold swing lower than the physical limit and the degree of Drain-induce Barrier Lowing is reduced. When junctionless ferroelectric field-effect-transistors are downscaled, it is insensitive to degradation by short-channel-effect. The last part discusses the characteristics of field-effect-transistor and capacitor through Sentaurus TCAD simulation and numerical analysis. It contains two different physical models which individually explain whether the ferroelectric effect is quasi-static or transient. The study compares the experimental data and proves the correctness of the two models.
The gate-all-around germanium channel nanowire junctionless ferroelectric field-effect-transistor with a simple manufacturing process can obtain good performance. Therefore, it has great potential in the development of low power consumption, high performance device in the future.

中文摘要 i
Abstract iii
Acknowledge v
Contents vi
Figure Captions vii
Chapter 1 1
Introduction 1
1-1 Challenge of Moore’s law 1
1-2 High mobility non-silicon channel materials 4
1-3 Epitaxy germanium on silicon-on-insulator 6
1-4 High dielectric constant gate oxide for germanium 8
1-5 Introduction of Junctionless field-effect transistor 11
1-6 Introduction of Steep subthreshold slope 13
1-7 Motivation 17
1-8 Dissertation Organization 22
Chapter 2 23
Mechanism of Junctionless Ferroelectric Field-Effect-Transistor 23
2-1 Principle of MOSFET 23
2-2 The Parameters Extraction of MOSFET 26
A. Threshold voltage (VTH) 26
B. Subthreshold swing (SS) 27
C. Drain Induce Barrier Lowering (DIBL) 27
2-3 Principle of Junctionless Transistor 29
2-4 Principle of ferroelectric effect 32
Chapter 3 38
Fabrication of Ge GAA Nanowire JL FE-FET 38
3-1 Device Fabrication Process 38
3-2 Device images Analysis 42
3-2-1 Scanning Electron Microscope (SEM) image of device structure 42
3-2-2 Focus Ion Beam (FIB) of the device structure 43
3-2-3 Transmission Electron Microscopy (TEM) image of device structure 45
3-3 Electrical Characteristics Analysis 48
Chaper 4 55
Simulation of Ge GAA Nanowire JL FE-FET 55
4-1 Device Structure and Parameter Setting 55
4-2 Result and Discussion : L-K model 57
4-3 Result and Discussion : Miller model 62
Chapter 5 64
Conclusion 64
Reference 65

Chapter 1
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Chapter 2
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Chapter 4
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