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作者(中文):蔣德佑
作者(外文):Chiang, Te-Yu
論文名稱(中文):閘堆疊與通道製程對多晶矽與多晶鍺電荷捕捉式快閃記憶體元件之操作特性研究
論文名稱(外文):Processes of Gate Stack and Channel on Operation Characteristics of Poly Si/Ge Charge-Trapping Flash Memory Devices
指導教授(中文):張廖貴術
指導教授(外文):ChangLiao, Kuei-Shu
口試委員(中文):黃文賢
沈昌宏
口試委員(外文):Huang, Wen-Hsien
Shen, Chang-Hong
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學號:107011540
出版年(民國):109
畢業學年度:109
語文別:中文
論文頁數:105
中文關鍵詞:快閃記憶體多晶矽多晶鍺電荷捕捉式穿隧氧化層
外文關鍵詞:Flash memoryPoly-SiPoly-GeCharge trappingTunneling layer
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隨著元件特徵尺寸微縮,如何以製程技術提升快閃記憶體元件的操作特性為目前極重要的課題之一,諸多方法已被提出並研究,例如:鍺材料的使用、介電材料之能帶工程、無接面元件、多向閘極與奈米線通道的結構應用等等。本篇論文分成三個部分,分別探討不同的電荷捕捉層材料以及不同結晶方式所形成之多晶矽三向式閘極快閃記憶體元件操作特性。另外也針對多晶鍺通道快閃記憶體元件之介面與穿隧氧化層進行製程研究以提升其操作特性。
第一部分研究氧化鉭混合氧化鋁並與氮化矽堆疊形成電荷捕捉層應用於多晶矽通道快閃記憶體元件上。由實驗結果得知,氧化鉭摻雜氧化鋁之電荷捕捉層,由於氧化鉭之深陷阱深度,使在沒有犧牲過大的電荷保持力之下,於抹除速度方面有小幅的提升。
第二部分著重於改善多晶鍺通道無接面電荷捕捉式快閃記憶體元件之介面與可靠度研究。為了解決鍺之介面問題,改善製程方式為解決方法之一。在這部分中,採用了電漿後氧化製程以及氮化處理來提升元件之操作特性。根據實驗結果,相較於電漿直接製程,電漿後氧化製程有效提升了操作速度,可靠度方面也有不錯的改善。經過氨電漿處理之樣品在整體特性上也具有明顯的提升。採用電漿後氧化製程配合氮化處理之樣品於綜合表現上較突出。
第三部分主要研究以固相結晶及雷射結晶形成之多晶矽與多晶鍺於快閃記憶體元件之特性差異。整體特性上,固相結晶多晶矽元件有最好的特性展現,推測雷射結晶將使其表面粗糙度及均勻性較差,導致後續閘極氧化層沉積出現薄膜厚度不均等問題,造成整體特性上的差異。然而多晶鍺元件在經過適當的電漿與製程處理後,整體特性與雷射結晶多晶矽元件差異不大。
With the shrinks of device feature size, how to improve the operating characteristics of flash memory device with process techniques is one of the urgent topics at present. Many approaches were proposed and studied, such as Germanium channel adoption, bandgap-engineered dielectrics, junctionless, multi-gate structures and nanowire channel, and so on. The thesis includes three parts to investigate the operating characteristics of Poly-Si flash memory devices formed by different charge trapping layers and various channels with different crystallization methods. In addition, the processes for the channel interface and tunneling layer of Poly-Ge CT flash memory device were also studied to improve operation characteristics.
In the first part, tantalum oxide doped with aluminium oxide and stacked with Si3N4 to form the trapping layer was applied to the Poly-Si flash device. It is found that erasing speed can be slightly improved without sacrificing too much retention characteristics by adopting TaAlO trapping layer, due to the deep trap level of tantalum oxide.
In the second part, the process study for interface and reliability improvement of Poly-Ge junctionless flash memory device is presented. In order to solve the interface problem of germanium, the process development is one of the feasible solutions. In this part, the plasma-post oxidation process (PPO) and nitridation treatments were proposed to improve operation characteristics of device. It is found that the PPO process effectively improves the operation speed and reliability. The overall characteristics of the samples treated by ammonia plasma are also significantly improved. As the whole, operation performance of the samples treated by the PPO process together with nitridation treatment is outstanding.
Third, Poly-Si and Poly-Ge formed by solid-phase and laser crystallization methods on operation characteristics of flash memory devices were studied. In terms of overall properties, the solid-phase crystalline Poly-Si sample has the best performance. Laser crystallization may cause poor surface roughness and uniformity, leading to non-uniform deposition and thickness of subsequent gate oxide, which causes variation in overall characteristics. However, through the process development, the overall characteristics of Poly-Ge sample can be similar to those of the laser crystalline Poly-Si ones.
摘要 I
ABSTRACT II
致謝 IV
目錄 V
圖目錄 VIII
表目錄 XII
第一章 序論 1
1.1. 非揮發性記憶體 1
1.1.1 快閃記憶體元件 2
1.1.2 浮動閘極式快閃記憶體 2
1.1.3 電荷捕捉式快閃記憶體 4
1.2. 多晶矽與多晶鍺薄膜電晶體 5
1.2.1 鍺材料特性與雷射退火 6
1.3. 多向式閘極結構與奈米線通道快閃記憶體 8
1.4. 高介電係數材料與能帶工程 9
1.4.1 高介電係數材料 9
1.4.2 能帶工程 10
1.5. 無接面快閃記憶體元件 12
1.6. 各章摘要 14
第二章 快閃記憶體元件製程與操作方法 27
2.1. 快閃記憶體元件製程 27
2.1.1 原子氣相沉積系統 27
2.1.2 感應耦合型電漿化學氣相沉積系統 29
2.2. 奈米線通道無接面快閃記憶體元件製程 30
2.3. 快閃記憶體基本操作原理與機制 31
2.3.1 載子穿隧機制 32
2.3.2 福勒-諾德海姆穿隧(Fowler-Nordheim Tunneling) 33
2.3.3直接穿隧(Direct Tunneling) 34
2.4. 電荷捕捉式快閃記憶體元件可靠度分析 35
2.4.1 元件耐久力 35
2.4.2 電荷保持力 36
第三章 介電層堆疊電荷捕捉層對多晶矽無接面式快閃記憶體元件特性影響之研究 47
3.1. 研究動機與背景 48
3.2. 實驗樣品製作流程與條件 49
3.3. 結果與討論 50
3.3.1 元件之汲極電流對閘極電壓特性圖 50
3.3.2 元件寫入與抹除特性 50
3.3.3 元件可靠度特性 52
3.4. 結論 53
第四章 應用電漿後氧化製程於穿隧氧化層以優化多晶鍺無接面電荷捕捉式快閃記憶體特性 65
4.1. 研究動機與背景 66
4.2. 實驗樣品製作流程與條件 67
4.3. 結果與討論 68
4.3.1 元件之汲極電流對閘極電壓特性圖 68
4.3.2 元件寫入與抹除特性 69
4.3.3 元件可靠度特性 70
4.4. 結論 72
第五章 雷射退火結晶之多晶矽/多晶鍺通道無接面電荷捕捉式快閃記憶體特性 81
5.1. 研究動機與背景 82
5.2. 實驗樣品製作流程與條件 83
5.3. 結果與討論 84
5.3.1 元件之汲極電流對閘極電壓特性作圖 84
5.3.2 元件的寫入與抹除特性 85
5.3.3 元件可靠度特性 86
5.4. 結論 87
第六章 總結 95
6.1. 結論 95
6.2. 未來展望 96

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