多使用者多輸入輸出系統與大規模陣列天線是能為下一世代行動通訊提供高吞吐量與資料量的重要技術。為了減少因大量天線的高解析度數位類比轉換器所造成的高成本和高功耗，量化預編碼藉由降低數位類比轉換器的解析度以達到能量能被限制在可忍受的範圍。為了解決現有演算法皆需要多次的遞迴以達到收斂，本篇論文針對一位元預編碼處理器提出星座點範圍結合增益控制晶格簡化演算法，利用星座點範圍設計應用在高調變訊號且使得接收端不需要額外處理所接收的訊號，結合傳統多輸入輸出搜尋方式與晶格簡化以降低複雜度。本論文所提出的預編碼演算法使用TSMC 40nm CMOS製程來實作成硬體。所提出的預編碼處理器適用於 64x4 多使用者多輸入多輸出系統與 64-QAM 傳送訊號。處理器的最高頻率為 153 MHz，功耗為 230 mW，最大資料吞吐量能達到 4.16 M 訊號/每秒。

Massive multi-user (MU) multiple-input and multiple-output (MIMO) systems becomes a crucial technique for the next generation communication systems due to the high throughput and reliability. With the increasing antennas equipped in the base station, power consumption turns into the high-priority challenge. Each antenna is connected to a pair of high resolution digital to analog converters (DAC) which resulting high power consumption. Thus, quantized precoding was proposed to utilize the low-resolution DAC for keeping power in a tolerable constraint. The quantized function brings about the nonlinear distortion which is hard to compensate. In this thesis, we propose a constellation range and gain-controlled lattice-reduction-aided algorithm for 1-bit precoding. Simulation results show that the proposed algorithm gains robust performance in high-QAM signaling as well as reduces the computation complexity by 60% when frame size equals to 100. We also design and implement an 1-bit precoding processor based on proposed algorithm. This chip is implemented by using TSMC 40nm COMS process technology. The processor supports the 64x4 MU-MIMO systems under 64-QAM transmitted symbols. The operating frequency of this chip is 153MHz and power consumption
is 230mW. The throughput of this chip achieve 4.16M symbols per second.

1 Introduction 1
1.1 Quantized Precoding for Massive Multi-user MIMO Systems 1
1.2 Research Motivation 3
1.3 Organization of This Thesis 4
1.4 Notations 4
2 Quantized Precoding and Lattice Reduction 7
2.1 System Model of Quantized Precoding for Massive Multi-user MIMO 7
2.2 Linear Quantized Precoding 9
2.2.1Linear Quantized Precoding Problem for 1-Bit DACs 11
2.2.2Linear Wiener Filter Precoding 11
2.3 Nonlinear Quantized Precoding 12
2.3.1Nonlinear Quantized Precoding Problem for 1-Bit DAC 12
2.3.2Nonlinear 1-Bit Sphere Precoding 13
2.3.3Binconvex 1-Bit Precoding 19
2.3.4Iterative Discrete Estimation 22
2.3.5Constellation Range Design for 1-Bit Precoding 25
2.4 Lattice Reduction 29
2.4.1LLL Algorithm 30
2.4.2Joint QR and LR Pre-processing with Enhanced Constant through-put LLL Algorithm 32
2.4.3Lattice-Reduction-Aided MIMO Systems 35
3 Proposed Nonlinear 1-Bit Precoding Agorithm 39
3.1 Constellation Range and Gain-Controlled Lattice-Reduction-Aided 1-Bit Precoding 39
3.2 Simulation Result and Analysis 43
4 VLSI Architecture 49
4.1 System Architecture 49
4.2 Gain-Controlled Joint QR and LR Pre-processing with ECTLLL Processor 51
4.3 Successive Interference Cancellation Processor 57
4.4 Timing Schedule 57
5 Implementation Result 61
5.1 Design Flow 61
5.2 Layout Hierarchy and Chip I/O 63
5.3 Chip Specification and Result 63
6 Conclusion 69
Reference 71

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