此論文探討應用穿隧元件機制來實現效能之電荷捕捉記憶體元件，這些穿隧機制包括能帶間量子穿隧與蕭特基能障穿隧。研究分析以二維元件模擬進行，探討操作原理與元件電性，著重穿隧行為對電荷捕捉記憶體之電流讀取特性與熱載子注入行為，並深入探索元件尺度微縮考量。其中，並利用暫態寫入分析，探討載子注入捕捉層後的開關讀取與注入寫入特性。首先發展創新的能帶間量子穿隧電荷捕捉記憶體元件，實現穿隧機制之效能電荷捕捉記憶體元件。繼而，與蕭特基能障電荷捕捉記憶體元件比較分析，並探求組合能帶間穿隧與蕭特基穿隧之非對稱蕭特基電荷捕捉記憶體元件的可行架構。
穿隧式電荷捕捉記憶體元件為創新型架構，能帶間穿隧除控制導通開關行為外，穿隧機制亦產生獨特的源極側熱電子注入特性，呈現低功耗與高注入效率表現。當通道長度微縮時，雖短通道效應影響穿隧導通與載子注入，藉由元件設計優化，可持續微縮且保有寫入與讀取特性。以能帶間穿隧或蕭特基穿隧作為元件開關機制，皆具備不同於傳統之源極端熱電子注入行為，蕭特基能障電荷捕捉記憶體元件，亦具備高注入效率表現。但相對而言，由於蕭特基元件導通電流較高，能更快完成熱電子注入寫入動作。至於非對稱或組合架構元件，依其設計參數與結構不同，可發展出與蕭特基元件相似或更效能的電荷捕捉記憶體元件。

This dissertation studies tunneling-based field-effect devices to serve as charge-trapping memory cells for energy-efficient applications, including band-to-band tunneling and Schottky barrier tunneling mechanisms. Using two-dimensional device simulations with appropriate models and parameters, this study explores the design and physics of proposed tunneling-based charge-trapping cells to elucidate their operating characteristics and cell scalability. Iterative programming was utilized to discuss the charge-coupled cells after unique source-side injections. This work first develops the innovative band-to-band tunneling charge-trapping cells, and then examines the Schottky barrier counterparts. Several potential tunneling-based structures were comprehensively investigated to determine proper selections of favorable energy-efficient cells.
For the innovative band-to-band tunneling charge-trapping memory cells, the tunneling determines current transport as well as hot-carriers generation to produce unique source-side injections for low-power operation and high-efficiency injection. It presents excellent cell scalability as device dimensions scaled down. Since both band-to-band tunneling and Schottky barrier tunneling generate particular source-side injections against traditional drift-diffusion cells, Schottky barrier cells also show high-efficiency injections. Relatively, the Schottky barrier devices enable a minimized time for cell programming due to the higher drain current. Other potential architectures, such as asymmetric Schottky barrier cells, can offer similar current and injection performance as those of symmetric Schottky barrier counterparts.

致謝 iii
Abstract iv
摘要 viii
Contents ix
List of Figures xii
List of Tables xxii
Chapter 1 Introduction 1
1.1 Tunneling-Based Energy-Efficient Devices 1
1.2 Charge-Trapping Flash Memories 2
1.3 Schottky Barrier Devices 3
1.4 Source-Side and Drain-Side Injection 4
1.5 Organization 5
Chapter 2 Device Structures and Physical Models in Numerical Simulations 10
2.1 Investigated Cell Structures and Key Parameters 10
2.2 Nonlocal Band-to-Band Tunneling Models 11
2.3 Schottky Barrier Tunneling 13
2.4 Lucky Electrons and Injected Currents 15
2.5 Iteration Methods for Cell Programming 16
Chapter 3 Tunneling Charge-Trapping Memory Cells 25
3.1 Source-Side Injection 25
3.2 Current Characteristics and Injection Efficiency 26
3.3 Bias-Dependent Source-Side Injection 27
3.4 Doping Concentration of Channel and Drain Regions 28
3.5 Thicknesses of Gate Dielectrics 30
3.6 Programming Characteristics 31
Chapter 4 Scaling of Tunneling Charge-Trapping Memory Cells 49
4.1 Effects of Scaling Channel Lengths 49
4.2 Effects of Scaling Drain Lengths 50
4.3 Programming Characteristics of Scaled Cells 52
Chapter 5 Schottky Barrier Charge-Trapping Memory Cells 65
5.1 Conduction Current and Injection Efficiency 65
5.2 Bias-Dependent Source-Side Injection 67
5.3 Schottky Barrier Heights 69
5.4 Programming Characteristics with Varied Schottky Barrier Heights 72
Chapter 6 Scaling of Schottky Barrier Charge-Trapping Memory Cells 96
6.1 Effects of Scaling Channel Lengths 96
6.2 Effects of Scaling Drain Lengths 98
6.3 Programming Characteristics of Scaled Cells 99
Chapter 7 Comparisons of Tunneling-Based Charge-Trapping Memory Cells 112
7.1 M-i-N and P-i-N Structures 112
7.2 M-i-M and M-i-N Structures 114
7.3 Iterative Programming of M-i-M/M-i-N/P-i-N Structures 116
Chapter 8 Conclusions 127
References 131

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