本論文主要希望發展出600V之4H-橫向型碳化矽高壓元件與隔離以供未來的BCD (Bipolar-CMOS-LDMOS)製程平台來使用，通過改善氧化製程來增強元件的性能，預期能做出比矽材料更低的特徵導通電阻且耐壓600V以上的橫向型高壓元件。
論文中使用RESURF結構及場平板設計橫向高壓元件，採用氧化後一氧化氮熱退火方式改善N型橫向擴散金氧半場效電晶體反轉通道，通道電子遷移率從6.54 cm^2/V∙s 提升至41.05〖 cm〗^2/V∙s，通過增加場氧化層的厚度改善表面電場分布，提升崩潰電壓。根據實驗結果，在漂移區長度為14μm下量測到的最佳LDMOS特徵導通電阻(Vg=30V)及崩潰電壓為252 mΩ*cm2、680V，而橫向PiN為9.27 mΩ*cm2、770V，同時利用電漿蝕刻以及P+溝槽離子佈植實現深溝槽隔離，達到隔離600V以上的效果。

This thesis mainly focuses on the development of 600V lateral 4H-SiC high-voltage devices and isolation to provide a BCD (Bipolar-CMOS-LDMOS) process platform for use in the future. The performance of these devices was improved by adjusting the oxidation process. It is expected to demonstrate lateral high-voltage devices with lower Ron,sp than those of silicon counterparts with a breakdown voltage of more than 600V.
In this thesis, RESURF structure and field plate are used in the design of lateral high-voltage devices. NO annealing has been used to improve the inversion channel for n-type LDMOS transistors. The electron channel mobility is increased from 6.54cm^2/V∙s to 41.05cm^2/V∙s. By increasing the thickness of the field oxide layer, the surface electric field profile is improved to increase the breakdown voltage. From the experiment results, the best Ron,sp (Vg=30V)and breakdown voltage of LDMOS are 252 mΩ*cm2 and 680V, while those of lateral PiN are 9.27 mΩ*cm2 and 770V with a drift region length of 14μm. In the meantime, plasma etching and P+ trench implantation are used to realize deep trench isolation capable of more than 600V isolation.

中文摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第一章 序論 1
1.1 寬能矽材料 4H-碳化矽 (4H-SiC) 1
1.2 碳化矽晶格結構 2
1.3 BCD製程及功率元件簡介 3
1.4 文獻回顧 4
1.5 研究動機與論文大綱 5
第二章 元件原理、設計與模擬 6
2.1 RESURF (Reduced Surface Field)原理 6
2.2 場平板 (Field Plate)結構 7
2.3 離子佈植技術 7
2.3.1 P型離子佈植 8
2.3.2 N型離子佈植 9
2.3.3 佈植後退火 10
2.4 碳化矽氧化層 10
2.4.1 乾氧製程 11
2.4.2 乾氧製程與NO熱退火 11
2.5 元件崩潰機制 12
2.5.1 累增崩潰 12
2.5.2 氧化層崩潰 13
2.6 元件設計與模擬 13
第三章 實驗製程 17
3.1 PiN元件製程 17
3.1.1 一般清潔(Normal Clean) 18
3.1.2 黃光微影製程(Lithography) 18
3.1.3 定義對準鍵(Define Alignment Key) 19
3.1.4 P阱離子佈植(P-well Implantation) 20
3.1.5 陽極P+離子佈植(Anode P+ Implantation) 21
3.1.6 陰極N+離子佈植(Cathode N+ Implantation) 21
3.1.7 蝕刻溝槽 (Trench Etch) 22
3.1.8 P+溝槽離子佈植(P+ Trench Implantation) 23
3.1.9 電性活化(Activation) 24
3.1.10 場氧化層(Field Oxide) 24
3.1.11 陽極歐姆接觸(Anode Ohmic Contact) 25
3.1.12 陰極歐姆接觸(Cathode Ohmic Contact) 26
3.1.13 快速熱退火(RTA) 26
3.1.14 墊金屬(Pad Metal) 26
3.2 LDMOS元件製程 28
3.2.1 閘極電極定義(Gate Electrode Definition) 29
第四章 實驗量測分析與探討 31
4.1 測試元件 31
4.1.1 歐姆接觸量測 31
4.1.2 NMOS電容 34
4.1.3 水平型NMOS 36
4.1.4 深溝槽隔離(DTI) Test Key 38
4.2 橫向型元件 40
4.2.1 順向量測 40
4.2.2 反向崩潰量測 44
4.3 文獻比較 46
第五章 結論與未來展望 48
參考文獻 49

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