本篇論文主要是探討超薄氧化鋅的研究，將氧化鋅從一般的薄膜厚度(數十到數百奈米)壓縮成一個原子層厚度，此材料在電性上會與一般薄膜厚度的氧化鋅產生極大的差異。我們期望超薄氧化鋅與其他材料形成蕭特基接面，進而組成電晶體，並且讓電晶體具有非常高的電流增益與開關特性。
本論文透過X光吸收光譜與X光螢光光譜的分析，顯示了超薄氧化鋅確實有成長在矽基板上。而在元件的製程中發現，超薄氧化鋅上熱蒸鍍金屬會導致金屬擴散，於是改用黏貼的方式製作論文中電晶體的集極與基極電極。
我們量測到元件的共射極電流增益β在BC接面逆偏0.2V且VBE為1mV的情況下，可達到57的數值，並且共基極電流增益α非常接近於1，驗證了以超薄氧化鋅當作電晶體基極的設計概念。若定義FOM為 β/V_BE V_CB，本論文能得到285000的數值，與其他篇論文比較高出不少，因此本論文製作之電晶體在低功耗與高增益上皆有非常好的表現。

This paper is mainly about the research of ultra-thin Zinc-Oxide. The thickness of bulk Zinc-Oxide is reduced from tens to hundreds of nanometers to only an atomic layer. There is great difference in electrical properties between ultra-thin Zinc-Oxide and bulk Zinc-Oxide. It was expected that the ultra-thin Zinc-Oxide may form Schottky contacts with other materials, which can be used to form a transistor, with extremely high current gain and proper switching characteristics.
The analysis of X-ray absorption spectrum and X-ray fluorescence spectrum, shows that the ultra-thin Zinc-Oxide was indeed deposited on the silicon substrate. Since thermal vapor deposition of metal on the ultra-thin Zinc-Oxide resulted in metal diffusion, through the ultra-thin Zinc-Oxide during the fabrication process, adhesion was used to fabricate the collector region and the base electrode.
When VCB was biased at 0.2V and VBE was biased at 1mV, a common emitter current gain β was measured to be 57 and a common base current gain α was measured to be very close to 1. It proves the concept of using ultra-thin Zinc-Oxide as the base of transistor. The FOM, which is defined as β/V_BE V_CB, was measured to be 285000 in this paper and it is higher than those in other researches. As a result, the transistor in this paper has great performance in both low power consumption and high current gain.

摘要......I
Abstract......II
致謝......III
目錄......V
圖目錄......VII
表目錄......X
第一章 前言......1
1.1 二維材料的發現......1
1.2 研究動機......2
1.3 論文章節架構......3
第二章 背景知識回顧......4
2.1 氧化鋅材料......4
2.1.1 氧化鋅基本性質......4
2.1.2氧化鋅結構......4
2.2 透明導電薄膜......9
2.3 氧化鋅照光影響......9
2.3.1 氧化鋅光致發光光譜......9
2.3.2 氧化鋅光電導......10
2.4 蕭特基接面與歐姆接面介紹......12
第三章 氧化鋅薄膜電晶體製作......17
3.1 氧化鋅薄膜製程......17
3.1.1 原子層沉積法(atomic layer deposition, ALD)原理介紹......17
3.1.2 氣流中斷法......19
3.1.3 氧化鋅薄膜品質檢測......20
3.2 元件設計與架構......24
3.2.1 雙極性電晶體特性推導......24
3.2.2 元件架構......28
3.3 實驗流程......31
3.3.1 n型矽基板製備......31
3.3.2 基板清洗......31
3.3.2 原子層沉積氧化鋅薄膜......32
3.3.3 基極電極製作......32
3.3.4 超薄氧化鋅電晶體製作......33
第四章 量測結果與討論......35
4.1量測儀器簡介......35
4.2量測方式......36
4.2.1 電極的歐姆測試......36
4.2.2 各接面電流對電壓量測......38
4.2.3 Gummel Plot......38
4.3量測結果......39
4.3.1電性量測 39
第五章 結論與未來展望......65
5.1結論與未來展望......65
5.1.1 結論......65
5.1.2 未來展望......66
參考文獻......67

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