隨著近年來資訊量的提升，高速序列通訊(High speed serial communication)的傳輸速率也不斷提升，然而隨著操作頻率的提升，使用光電轉換介面以及光纖取代傳統銅質導線作為傳輸通道，其低耗損高頻寬及低串音干擾的特性可以有效改善傳輸品質，因此此論文中則著重於光纖通訊系統中接收端的前端類比放大器。
在第一章中，簡述光纖通訊的優點以及本論文之研究方向，並且將光纖通訊的架構簡單的介紹。
在第二章中，介紹設計的電路在光纖通訊中之應用，所使用的架構以及展頻技巧，最後簡述設計流程。
第三章中，使用IHP 0.13 m SiGe BiCMOS 製程設計轉阻放大器，使用並聯電阻回授架構以達到合適的頻寬以及雜訊，並且藉由回授以及鈍化電阻改善異質接面雙極性電晶體的線性度。量測結果中，轉阻增益達到47dBΩ，頻寬50GHz，在NRZ 調變下傳輸速率達到64Gb/s，PAM4 調變下則為32Gbaud。
第四章中，使用TSMC 16 nm FinFET 製程設計轉阻放大器，採用串疊調節架構作為前級電路，擁有電感性以及較小的輸入阻抗以提高頻寬，後面使用疊接的差動對以及緩衝器作為寬頻的放大級電路，其中藉由控制電壓調控鈍化電阻阻值在量測時可以小幅調整高低頻增益的平衡，模擬結果達到65 dBΩ，頻寬17GHz，PAM4 調變下傳輸速率可達到40 Gb/s。
第五章中，使用TSMC 40 nm CMOS 製程設計光通前端類比放大器，前端的轉阻放大器採用電阻並聯回授的架構，並與另一個平衡偏壓用的轉阻放大器輸入後面的放大級電路，放大級電路使用架構與第四章相似，但由於整體設計轉為單端輸入，為了不使輸入端的偏壓誤差以及製程誤差造成後端的電路無法正常操作，使用誤差抵消電路利用負回授的特性將偏壓穩定。在模擬結果中轉阻增益達到50 dBΩ，頻寬20 GHz，使用PAM4 調變達到25 Gbaud 的傳輸速率。
第六章中，總結上述工作內容以及簡述未來發展的方向，除了類比前端放大器本身效能，透過對整體系統的考量為前端電路增加更多需要的功能，以及設計更多後級的電路與之整合，完成光電收發模組。

With the continuous growth of technology in recent years, the data rate of high speed serial communication has increased rapidly. The optical fibers with OE interface replace the traditional copper wires as transmission channels to fulfill the need of high data rate. The characteristics of low loss, high bandwidth and low crosstalk interference can effectively improve the transmission quality, so this thesis focuses on the front-end analog amplifiers of the receiver in the optical fiber communication system.
Chapter 1 describes the advantages of optical fiber communication and the research direction of this thesis. The architecture of optical fiber communication is also introduced.
Chapter 2 introduces the application of the proposed circuits in optical communications, including the circuit topology and the bandwidth extension technique, and finally briefly describes the design procedure.
In chapter 3, we propose a 64-Gb/s transimpedance amplifier in IHP SiGe 0.13μm process, using common-collector and common-emitter amplifiers with shunt feedback resistor. The circuit achieves a transimpedance gain of 47 dBΩ and a bandwidth 50 GHz in simulations. The measured data rate is up to 64 Gb/s with NRZ modulation, and 32 Gbaud with PAM-4 modulation.
In chapter 4, a 20-Gbaud transimpedance amplifier in TSMC 16nm FinFET process is presented, using a modified RGC configuration as the input stage and cascode differential pair as the gain stage. The circuit achieves a transimpedance gain of 65 dBΩ and a bandwidth of 17 GHz. The simulated data rate is up to 40-Gbaud with PAM-4 modulation.
In chapter 5, a 25-Gbaud transimpedance amplifier in TSMC 40nm CMOS process is presented, using shunt feedback topology as the input stage and cascode differential pair as gain stage. The circuit achieves a transimpedance gain of 50 dBΩ and a bandwidth of 20 GHz. The simulated data rate is up to 25-Gbaud with PAM-4 modulation.
Chapter 6 gives the conclusion of previous chapters, and provides recommendations to the future works.

第1 章 緒論 ........................................ 11
1.1 研究背景跟動機 ................................. 11
1.2 光纖通訊系統簡介................................ 12
第2 章 高頻轉阻放大器設計架構及展頻技巧............... 13
2.1 光纖通訊所使用之轉阻放大器....................... 13
2.2 轉阻放大器架構.................................. 14
2.3 展頻技巧........................................ 19
2.4 章節總結........................................ 25
第3 章 64GB/S 轉阻放大器 ............................ 26
3.1 IHP SIGE 0.13 ΜM BICMOS 製程.................... 26
3.2 設計電路介紹..................................... 26
3.3 模擬及量測結果................................... 27
3.4 結果與討論....................................... 32
第4 章 15 GBAUD 可調式轉阻放大器....................... 35
4.1 TSMC 16NM FINFET 製程............................ 35
4.2 設計電路介紹...................................... 36
4.2.1 改良串疊調節架構(Modified RGC).................. 37
4.2.2 差動對及緩衝器(Differential Pair and Buffer).... 38
4.2.3 等化器 ........................................ 39
4.3 模擬結果 ........................................ 39
4.4 結果與討論....................................... 43
第5 章 25 GBAUD 光纖通訊類比前端放大器................. 44
5.1 設計電路介紹..................................... 44
5.1.1 電阻並聯回授轉阻放大器.......................... 45
5.1.2 增益可調放大器、等化器及輸出緩衝器................ 46
5.1.3 直流誤差抵消電................................. 48
5.2 模擬結果......................................... 50
5.3 結果與討論...................................... 54
第6 章 結論及未來展望................................ 55
6.1 結論............................................ 55
6.2 未來展望........................................ 56
參考文獻............................................ 57

[1] K. Vasilakopoulos, S. P. Voinigescu, P. Schvan, P. Chevalier and A. Cathelin, "A 92GHz bandwidth SiGe BiCMOS HBT TIA with less than 6dB noise figure," IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, Boston, MA, 2015, pp. 168-171.
[2] Sung Min Park and C. Toumazou, "A packaged low-noise high-speed regulated cascode transimpedance amplifier using a 0.6 µm N-well CMOS technology," Proceedings of the 26th European Solid-State Circuits Conference, Stockholm, Sweden, 2000, pp. 431-434.
[3] C. Talarico, G. D'Amato, G. Avitabile, G. Piccinni and G. Coviello, "A systematic design approach for nanoscale inductor-less regulated cascode stages," 29th Symposium on Integrated Circuits and Systems Design (SBCCI), Belo Horizonte, 2016, pp. 1-5.
[4] L. B. Oliveira, C. M. Leitao and M. M. Silva, "Noise performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors," IEEE Trans. Circuits and Systems I: Regular Papers, vol. 59, no. 9, pp. 1841-1848, Sept. 2012.
[5] S. Shekhar, J. S. Walling and D. J. Allstot, "Bandwidth Extension Techniques for CMOS Amplifiers," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2424-2439, Nov. 2006.
[6] J. Jin and S. S. H. Hsu, "A Miniaturized 70-GHz Broadband Amplifier in 0.13-μm CMOS Technology," in IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 12, pp. 3086-3092, Dec. 2008.
[7] M. Tang et al., "A 56-Gb/s PAM4 Continuous-Time Linear Equalizer with Fixed Peaking Frequency in 40-nm CMOS," IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Chengdu, China, 2019, pp. 89-90.
[8] C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF ICs," in IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.
[9] S. Bhagavatheeswaran, T. Cummings, E. Tangen, M. Heins, R. Chan and C. Steinbeiser, "A 56 Gb/s PAM-4 linear transimpedance amplifier in 0.13-μm SiGe BiCMOS technology for optical receivers," IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Miami, FL, 2017, pp. 1-4, doi: 10.1109/CSICS.2017.8240445.
[10] B. Parvais et al., "FinFET technology for analog and RF circuits," 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, 2007, pp. 182-185.
[11] K. R. Lakshmikumar et al., "A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links," in IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3180-3190, Nov. 2019, doi: 10.1109/JSSC.2019.2939652.
[12] Y. Xie et al., "Low-Noise High-Linearity 56Gb/s PAM-4 Optical Receiver in 45nm SOI CMOS," IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4, doi: 10.1109/ISCAS.2018.8351224.
[13] B. Goll, R. Swoboda and H. Zimmermann, "Receiver Chip in 0.6µm BiCMOS with AGC and LVDS Output Driver," Austrochip Workshop on Microelectronics (Austrochip), Linz, 2017, pp. 18-22, doi: 10.1109/Austrochip.2017.16.
[14] M. Maadani and M. Atarodi, "A Low-Area, 0.18μm CMOS, 10Gb/s Optical Receiver Analog Front End," IEEE International Symposium on Circuits and Systems, New Orleans, LA, 2007, pp. 3904-3907, doi: 10.1109/ISCAS.2007.378547.
[15] T. Yao, D. Li, Y. Xie, P. Y. Chiang and Z. Hong, "A Low-Noise 56Gbps PAM-4 Linear Optical Receiver in 40nm CMOS," 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, 2018, pp. 1-3, doi: 10.1109/ICSICT.2018.8565734.
[16] K. Honda, H. Katsurai, M. Nada, M. Nogawa and H. Nosaka, "A 56-Gb/s Transimpedance Amplifier in 0.13-µm SiGe BiCMOS for an Optical Receiver with -18.8-dBm Input Sensitivity," IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Austin, TX, 2016, pp. 1-4, doi: 10.1109/CSICS.2016.7751018.
[17] S. G. Kim et al., “A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology, ” IEEE A-SSCC, KaoHsiung, 2014, pp. 357-360.
[18] 陳聖文, “應用於光連結系統之高速前端電路與光電介面交換機設計,”國立清華大學電子工程研究所碩士論文,2012。
[19] 邱柏崴, “光連結系統之高速收發機電路與交換機設計及量測,”國立清華大學電子工程研究所碩士論文,2013。
[20] 李彥鋒, “高速光通訊前端電路設計宇收發元件等效電路建立,”國立清華大學電子工程研究所碩士論文,2016。
[21] 王顥儒, “光通訊高速接收端電路設計,”國立清華大學電子工程研究所碩士論文,2017。
[22] 陳泰均, “高速分散式放大器與光通訊驅動放大器設計,”國立清華大學電子工程研究所碩士論文,2018。
[23] 吳明政, “高速光通訊接收端之前端放大電路設計,”國立清華大學電子工程研究所碩士論文,2018。