在現今通訊電路系統中,為了達到更高的傳輸效率,往往必須增加訊號傳輸頻寬,這也使得訊號頻寬成為在通訊電路設計領域中變得越來越重要,另外依照現今頻帶使用狀況而言,第五代行動通訊頻帶定型的同時,也確定了為了達到更大的頻寬,訊號頻率的增加也成為電路設計與半導體製程研發的的重點趨勢。

隨著電子產品的應用漸漸廣泛,早年高成本高單價的半導體製程慢慢不被市場接受也不利於通訊產品的普及,也因為如此,成本低廉的CMOS製程也逐漸在傳統上因頻率與輸出功率等問題而較不具競爭優勢的通訊收發機領域受到重視,如果成本低廉的CMOS製成能夠克服頻率障礙,則能藉由製成優勢達到具備高整合度的通訊晶片,對通訊電路的應用將會有很大的幫助.

綜合上述原因,本論文嘗試以CMOS製成實現數百GHz至THZ頻率等級(0.3-3THz)的訊號產生器,期望能在訊號頻率與相位雜訊,訊號功率間取得平衡,以實現CMOS製成在高頻段通訊領域上的應用.

為了克服CMOS製成在高頻訊號表現上的缺陷,本論文中嘗試的訊號產生器均採用高頻諧波項訊號而非一般基頻訊號,此方法可以使電路更輕鬆產生較高頻訊號,但也同時產生出訊號受其他諧波項的干擾進而影響相位雜訊等等問題,故在本論文後段更著重於利用鎖相迴路電路來進行訊號鎖定同時降低相位雜訊,這也使得THz等級的鎖相迴路成為本論文的重點嘗試與挑戰.

In today’s communication system, communication signal bandwidth becomes wider than before for higher information exchanging speed, making bandwidth becomes more and more important in RF communication circuit design. As the fifth communication generation growth, increasing the signal frequency becomes a critical trend in both circuit design and semiconductors production development.

As the applications of various electronic items become more and more ubiquitous, the current market has stricter demand in production cost than early years. As a result, some advanced and expensive semiconductor processes are not suitable for prevailing in current market. Due to this reasons, low-cost semiconductor process like CMOS are valued in RF transceiver design today. Although these processes were unsuitable before due to their lower saturation frequency and inadequate power delivered, these problem have been substantially solved by advanced technology.
If cheaper process like CMOS could get over the frequency problem, people can use the advantage of CMOS to achieve highly-integrated communication chips which will really benefits the applications of communication.

As mentioned, this thesis trying to realize signal generators with operation frequency at hundreds GHz to THz level with CMOS process, expect to get a well balance within frequency, phase noise and signal power in order to achieve the application of CMOS in high-frequency communication field.

In order to get over the defects of CMOS in high frequency performance, all the signal generators in this thesis didn’t use fundamental signal as analog circuit design but high-order harmonic signal. With this method, the circuit could get higher frequency signal easier, but at the same times would inevitably produce some problems like desire signal be affected by other harmonic, impacting phase noise performance, so in later paragraph of this thesis, we focus on phase-locked loop(PLL) to locking signal and reduce phase noise, this make THz-level PLL became a important challenge in this thesis.

摘要 i
ABSTRACT ii
Chapter 1 Introduction 1
1.1 RF system and millimeter wave 1
1.2 Transceiver Architecture 3
1.3 LO signal issue 4
1.4 THz application 7
Chapter 2 A 200 GHz 16 QAM Receiver 8
2.1 Quadrature amplitude modulation 8
2.2 A 200GHz QAM Receiver 11
2.3 200GHz frequency doubler with quadrature output 12
2.3.1 frequency doubler 13
2.3.2 buffer amplifier and neutralization technique 16
2.3.4 quadrature phase shifter 18
2.4 layouts and measurement results 24
Chapter 3 340GHz voltage controlled oscillators and phase locked loops 33
3.1 basic mechanism and analysis of PLL 33
3.1.1Analysis PLL in frequency domain 35
3.1.2 Settling behavior 43
3.1.3 loop bandwidth concerns 44
3.1.4 PLL with second order LPF 52
3.2 340GHz PLL 57
3.2.1 comparison of ILFD and miller divider 58
3.2.2 miller divider design 68
3.2.3 340 GHz push-push oscillator 73
3.2.4 340GHz quadra-push oscillator 76
3.2.5 charge pump design 79
3.2.6 340GHz PLL design 82
3.2.7 simulation result of PLL 88
3.2.8 measurement result of PLLs 91
Chapter 4 conclusion and future work 103
Reference 105

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