本篇論文，是以4H-SiC為材料，製作橫向型高崩潰電壓元件，如PiN二極體、LDMOS，並應用深溝槽隔離 (Deep Trench Isolation, DTI)、double RESURF (Reduced Surface Field) 原理與氧化後NO退火製程於元件研製。
在元件設計中，double RESURF的原理，能夠幫助空乏區於漂移區垂直以及水平方向充分展開，因此在提高漂移區濃度以降低導通電阻的同時，能夠維持相同的崩潰電壓。同時，也採取了氧化後NO退火的製程，來進一步改進導通電阻值。
根據量測的結果，PiN二極體最佳特徵導通電阻為1.57 mΩ-cm2，崩潰電壓為975 V；LDMOS最佳特徵導通電阻為133 mΩ-cm2，崩潰電壓為809 V；DTI測試結構可以達成945 V 電路高低壓區域隔離的效果。由上述結果可知，本實驗所製作的PiN、LDMOS元件其BFOM (Baliga's Figure Of Merit) 超過了Si極限，以及那些以Si製作的橫向型元件，再再顯現了SiC橫向型元件優異的發展潛力。

In this study, deep trench isolation (DTI), double reduced surface field (RESURF) concept, and post-oxidation NO annealing were applied to design and fabrication of lateral high voltage devices in 4H-SiC, such as PiN diode and LDMOS.
In the design of the fabricated devices, the concept of double RESURF is employed, which helps depletion of the drift region from both top and bottom sides. As a result, the drift region concentration can be increased with the decrease in on-resistance while keeping the same breakdown voltage. In the meantime, post-oxidation NO annealing is also employed in the process to improve the on-resistance.
According to the measurement results, the best specific on-resistance is 1.57 mΩ-cm2 for PiN diodes and breakdown voltage achieved is 975 V. For LDMOS, the best specific on-resistance is 133 mΩ-cm2 with a breakdown voltage of 809 V. As for DTI test structure, which isolates high side and low side functions of the circuits, can isolate 945 V. Based on these result, the Baliga’s Figure Of Merit (BFOM) of the PiN diode and LDMOS demonstrated in this work has surpassed the Si limit, and exceed those of the Si lateral devices, which shows the excellent potential of SiC lateral devices.

摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 viii
第一章 序論 1
1.1 前言 1
1.2 碳化矽材料簡介 2
1.3 文獻回顧 4
1.3.1 Baliga’s Figure Of Merit (BFOM) 4
1.3.2 RESURF (Reduced Surface Field) 理論 5
1.3.3 場平板 (Field plate) 7
1.3.4 氧化後退火 8
1.3.5 橫向型SiC元件 10
1.3.6 動機與論文大綱 11
第二章 元件介紹與實驗設計 13
2.1 磊片結構 13
2.2 元件介紹 14
2.2.1 TLM元件 15
2.2.2 PiN元件 16
2.2.3 深溝槽隔離 (Deep Trench Isolation, DTI) 測試結構 18
2.2.4 LDMOS 20
2.2.5 MOSC 22
2.3 離子佈值技術 23
2.3.1 P型井 (p-well) 離子佈值 23
2.3.2 陽極、深溝槽側壁P型離子佈值 24
2.3.3 陰極N型離子佈值 25
2.3.4 P-top 離子佈值 26
2.3.5 佈值後退火 28
2.4 氧化製程 28
第三章 元件製程 29
3.1 一般清洗 (normal clean) 29
3.2 黃光顯影製程 (Lithography & Development) 30
3.3 殘餘光阻去除 (Residual Photoresist Removal) 30
3.4 定義對準標記 (Define Alignment Key) 30
3.5 離子佈植 (Ion Implantation) 31
3.6 深溝槽隔離 (DTI, Deep Trench Isolation) 32
3.7 電性活化 (Activation) 33
3.8 氧化製程 (Oxidation) 34
3.9 陽極與基極歐姆接觸 (Anode & Body ohmic contact) 35
3.10 陰極與源極汲極歐姆接觸 (Cathode, Source & Drain ohmic contact) 35
3.11 墊金屬與閘極金屬 (Pad metal & Gate metal) 36
第四章 量測與結果分析 36
4.1 基本介紹 36
4.2 MOSC 39
4.3 TLM 42
4.4 二極體 50
4.4.1 順向特性 50
4.4.2 逆向特性 54
4.5 DTI測試結構 58
4.5.1 逆向特性 58
4.6 LDMOS 60
4.6.1 順向特性 60
4.6.2 逆向特性 63
4.7 文獻比較 67
第五章 結論及未來展望 68
參考文獻 70

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