近年來，隨著物聯網(IOT)時代的來臨，應用於低成本、低耗能、高速與高容量的非揮發性記憶體之產品迅速增加及日益擴展，其中，快閃記憶體(NAND Flash)因具有低成本以及高容量之特性，所以成為當今主流的非揮發記憶體，但由於快閃記憶體(NAND Flash)具有較低壽命、高寫入電壓及當製成微縮時生產之瓶頸，且操作時速度相對偏慢，因為必須開發下世代之非揮發記憶體。
在下世代的非揮發性記憶體當中(例如:ReRAM、STT-MRAM…等)非常適合用於穿戴式裝置中，其中，由於電阻式記憶體(ReRAM)具有快速讀取和低供給電壓之特性，此外，其低寫入功耗、小面積、以及具有邏輯製成相容性，可降低製作成本。所以非常適合應用於內嵌式裝置。隨著製成微縮，電阻式記憶體(ReRAM)之阻值的漂移量也隨之增加，造成高阻態(HRS)及低阻態(LRS)之比值(R-ratio)縮小。
在本碩士論文中將探討電阻式記憶體(ReRAM)在存取上會面臨之挑戰，並提出一電壓感測放大器電路解決以下問題，以提升讀取效能:
1. 隨著製成微縮，使得R-ratio變小，導致讀取時之感測裕度(sensing margin)變小。
2. 隨著製成微縮，使得R-ratio變小，導致需要更長之讀取時間。
3. 由於讀取電壓過高時，將造成讀取干擾(Read disturb)問題。但傳統電壓感測放大器操作於低電壓讀取時良率下降。
因此，在此篇論文中提出應用於非揮發性記憶體具增益增強回授架構之小偏移電壓感測放大器(SOGEF-VSA)。我們提出的SOGEF-VSA可容忍3倍以下之讀取電壓及與傳統電壓感測放大器相比可容忍之小偏移電壓量提升8倍，在正常操作電壓1V以及不同位元線(Bitline)長度時，可以減少2~2.83倍之讀取速度，且可增加15.74倍感測裕度與降低位元線(Bitline)對讀取速度的影響。
我們採用台積電55奈米製程之電阻式記憶體來實作我們提出的架構。在正常操作電壓為1V下，且可以正常操作於讀取電壓為100mV時，另外，量測提出之電路讀取速度為1 ns。

In recent years, with the coming of the Internet of things (IOT) era. Applied to low cost, low energy, high speed and high capacity of non-volatile memory products increased rapidly, and increasingly expanded. Among them, NAND Flash memory has become the mainstream non-volatile memory due to its low cost and high capacity. However, NAND Flash memory has low lifetime, high write voltage, production bottleneck when it faces difficulties of scaling down to nanometer scale, and the operation speed is relatively slow. Therefore, the next generation of nonvolatile memory must be developed.
In the next generation of non-volatile memory (e.g., ReRAM, stt-mram...) ReRAM is very suitable for portable devices. Since ReRAM has the characteristics of fast read time and low supply voltage, as well as low write power consumption, small area and logic compatibility, it can reduce production cost. So it is very suitable for embedded devices. As the scaling down to nanometer scale, the ReRAM drift increases and the R-ratio decreases.
In this master's thesis, the challenges of using the ReRAM will be explored, and a voltage-sensing amplifier circuit will be proposed to solve the following problems to improve reading efficiency:
1. As the scaling down to nanometer scale, the R-ratio becomes smaller, resulting in smaller sensing margin in read mode.
2. As the scaling down to nanometer scale, the R-ratio decreases, which leads to a longer read time.
3. It may cause Read disturb due to the high Read voltage. But that yield of the conventional voltage sense amplifier is decrease when operating at the low Read voltage.
Therefore, A Small Offset Sense Amplifier with Gain Enhanced Feedback Scheme for Non-volatile Memories is proposed in this paper.
Our proposed SOGE-VSA can tolerate a read voltage of less than 3 times and a small offset voltage of 8 times higher than that of traditional voltage-sensing amplifiers. When the normal operating voltage is 1V and Bitline length is different, the read speed can be reduced by 2-2.83 times, and the sensing margin can be increased by 15.74 times. The influence of Bitline on the read speed can be reduced.

摘要-i
Abstract-iii
致謝-v
Contents-vi
List of Figures-viii
List of Tables-x
Chapter 1 Introduction-1
1.1 The Role of Memory in SoC products-1
1.2 Memory Landscape-2
1.3 Challenges of Flash Memory-5
1.4 Emerging Non-Volatile Memories-7
Chapter 2 Characteristic of Contact-RRAM-12
2.1 Structure of Contact-RRAM-12
2.2 Switching Mechanism-14
2.3 Write operation-14
2.4 Read operation-16
2.5 Distribution of CRRAM-17
Chapter 3 Design Challenges of Small Offset & High Speed-19
3.1 Structure and Operations of Conventional Sensing Amplifier Schemes-19
3.2 Design Challenges-21
3.2.1 Threshold Voltage in Process-21
3.2.2 Issues of CRRAM-22
3.3 Previous Arts-23
Chapter 4 Proposed Sensing Schemes and Analysis-30
4.1 Proposed Sense Amplifier-30
4.1.1 Motivation and Concept of Proposed Sense Amplifier-30
4.1.2 Structure of Proposed Sense Amplifier-32
4.1.3 Operations of Proposed SOGEF-VSA-33
4.2 Analysis and Comparison-36
4.2.1 Efficiency of Margin Enhancement-36
4.2.2 Tolerance of low R-ratio and Read Voltage-37
4.2.3 Access time (TAC) Improvement-39
4.2.4 Read Energy Consumption Reduction-40
4.2.5 Capacitor Analysis-41
4.2.6 Yield Analysis-42
Chapter 5 Measurement Results and Conclusion-43
5.1 CRRAM Macro-43
5.2 Design for Test-chip-45
5.3 Measurement results-47
5.4 Conclusions and Future Work-51
Reference-54

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