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作者(中文):羅嘉諄
作者(外文):Lo, Chia-Chun
論文名稱(中文):考慮位移量與線長優化之混合列高設計之混合高度元件擺置合法化
論文名稱(外文):Mixed-Height Cell Placement Legalization for Mixed-Row-Height Designs Considering Displacement and Wirelength Optimization
指導教授(中文):王廷基
指導教授(外文):Wang, Ting-Chi
口試委員(中文):麥偉基
陳勝雄
張豐願
口試委員(外文):Mak, Wai-Kei
Chen, Sheng-Hsiung
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:106062537
出版年(民國):108
畢業學年度:107
語文別:英文
論文頁數:39
中文關鍵詞:晶片設計自動化標準元件擺放合法化混合列高
外文關鍵詞:EDAPDAILPPlacementLegalization
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傳統的標準元件庫是由多種高度相等的功能標準元件所組成,標準元件被
擺置時必須對齊擺置區域中列上的擺置空間單位,其目的為將設計流程及優化簡
單化。在較為先進的標準元件庫中,整數倍列高的標準元件被設計以符合不同的
設計需求,擺置空間仍由單一列高組成。在最先進的製程中,混合列高的設計被
提出以克服快速成長的設計複雜度,不同高度的列可以導致較佳的標準元件密度
與晶片效能。其中單一列高的標準元件之高度可以被設計為不同之列高,多列高
度可以被設計為不同列高之組合,標準元件之高度會為面積與功耗等不同面向帶
來不同之優缺點。混合列高設計的出現大幅度地增加了標準元件擺置合法化的難
度,其原因為與以往大相逕庭的擺置列高規劃與不同高度之標準元件於擺置空間
中的相互影響。
據我們所知,尚未有任何商用軟體可以解決混合列高設計中的標準元件合
法擺置之問題,因此在本篇論文中,我們提出一個以整數線性規劃及線性規劃為
主軸的方法。首先,將整個擺置區域切割成多個等大的方型區域,接著使用整數
線性規劃擺置每個方型區域中的標準元件,我們提出的整數線性規劃的優化目標
允許小部分的標準元件不被擺置,而這些標準元件會由後續的步驟被合法擺置。
最後,我們使用線性規劃進一步減少總體標準元件的位移量與總體線長。提出之
方法的穩健性會在實驗結果的章節中進一步探討。
A traditional standard cell library consists of different functional cells with the same height for easier design and optimization, while cells are required to be aligned to specified placement sites in rows. In modern circuits, standard cells of multiple-row heights are designed to meet various design requirements, but placement rows are still designed with a uniform height. In most advanced nodes, mixed-row-height designs have been introduced to overcome the fast-growing design complexity of technology scaling. Rows with different heights are used for better design density and performance. Cells can be designed with differing heights utilizing different number of fins. Single-row-height cells are designed with various row heights with different advantages and shortcomings, while multiple-row-height cells are designed with height of combinations of different row heights. Mixed-row-height designs greatly increase the difficulty of placement legalization due to the very different row configuration and the placement dependency incurred by the multiple-row-height cells. In this thesis, we study a placement legalization problem for mixed-row-height designs. But to the best of our knowledge, no existing commercial tools can solve such a legalization problem of mixed-row-height designs. To deal with this challenge, we propose an approach based on integer linear programming (ILP) and linear programming (LP). First, we divide the entire placement region into uniform bins. Next, placement in each bin can be done using ILP in parallel. Instead of requiring all cells being placed legally by ILP which may be infeasible or too time consuming, our ILP formulation allows a small amount of cells to be left unplaced. These unplaced cells can be placed legally in the subsequent stage using the method in [1], which is inspired by [3]. Finally, the total cell displacement and wirelength are further improved using LP. The robustness of our approach is evaluated by extensive experiments.
1 Introduction 1
1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previous Related Works . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Major Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Preliminaries 5
2.1 Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Proposed Approach 8
3.1 Overall Flow of our Approach . . . . . . . . . . . . . . . . . . . . . 8
3.2 ILP-based Legalization . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1 Enumerating candidate positions . . . . . . . . . . . . . . . 10
3.2.2 ILP formulation . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3 Time complexity analysis . . . . . . . . . . . . . . . . . . . . 16
3.2.4 Parallelization . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Post-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 LP-based Re nement . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Experimental Results 24
4.1 Environment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Benchmark and Parameter Setup . . . . . . . . . . . . . . . . . . . 24
4.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.1 Comparison between Di erent Parallelization Methods of
ILP-based Legalization . . . . . . . . . . . . . . . . . . . . . 30
4.3.2 Comparison between LP-based Re nement with and with-
out Parallelization . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.3 Evaluation of the Robustness of Our Approach . . . . . . . . 33
5 Conclusion 36
References 37
[1] P.-S. Chiu, Placement Legalization for Designs with Mixed-Height Cells and Rows," Master's thesis, National Tsing Hua University, Hsinchu, Taiwan, 2019.
[2] W. Chow, C. Pui, and E. F. Y. Young, Legalization algorithm for multiple row height standard cell design," in Proc. of Design Automation Conference, pp. 83:1-83:6, 2016.
[3] S.-H. Baek, H.-Y. Kim, Y.-K. Lee, D.-Y. Jin, S.-C. Park, and J.-D. Cho, Ultrahigh density standard cell library using multi-height cell structure," in Proc. of SPIE - The International Society for Optical Engineering, 2008.
[4] P. Spindler, U. Schlichtmann, and F. M. Johannes, Abacus: Fast legalization of standard cell circuits with minimal movement," in Proc. of International Symposium on Physical Design, pp. 47-53, 2008.
[5] C. Wang, Y. Wu, J. Chen, Y.-W. Chang, S. Kuo, W. Zhu, and G. Fan, An e ffective legalization algorithm for mixed-cell-height standard cells," in Proc. of Asia and South Paci c Design Automation Conference, pp. 450-455, 2017.
[6] Y. Lin, B. Yu, X. Xu, J.-R. Gao, N. Viswanathan, W.-H. Liu, Z. Li,
C. J. Alpert, and D. Z. Pan, Mrdp: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes," in Proc. of International Conference on Computer-Aided Design, pp. 7:1-7:8, 2016.
[7] H. Li, W.-K. Chow, G. Chen, E. F. Y. Young, and B. Yu, Routability-driven and fence-aware legalization for mixed-cell-height circuits," in Proc. of Design Automation Conference, pp. 150:1-150:6, 2018.
[8] J. Chen, Z. Zhu, W. Zhu, and Y.-W. Chang, Toward optimal legalization for mixed-cell-height circuit designs," in Proc. of Design Automation Conference, pp. 52:1-52:6, 2017.
[9] C.-Y. Hung, P.-Y. Chou, and W.-K. Mak, Mixed-cell-height standard cell placement legalization," in Proc. of Great Lakes Symposium on VLSI, pp. 149-154, 2017.
[10] S. Goto, An effcient algorithm for the two-dimensional placement problem in electrical circuit layout," IEEE Transactions on Circuits and Systems, vol. 28, no. 1, pp. 12-18, 1981.
[11] LLC, Gurobi Optimization, Gurobi optimizer reference manual," 2018.
[12] D. Leonardo and M. Ramesh, Openmp: An industry-standard api for shared-memory programming," IEEE Computational Science and Engineering, vol. 5, no. 1, pp. 46-55, 1998.
[13] I. S. Bustany, D. Chinnery, J. R. Shinnerl, and V. Yutsis, \Ispd 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement," in Proc. of International Symposium on Physical Design, pp. 157-164, 2015.
[14] C. Huang, H. Lee, B. Lin, S. Yang, C. Chang, S. Chen, Y. Chang, T. Chen, and I. Bustany, Ntuplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, pp. 669-681, March 2018.
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