受益於先進製程的晶片同時對暫態錯誤更為敏感，因此必須對暫態錯誤進行功能故障
模擬，以評估電路的脆弱性。然而，由於電路的複雜性和大量的暫態錯誤，模擬過程非常
耗時。為提高模擬效率，採用降低錯誤方法去除過程中不必要的故障。這些方法通常基
於Architecturally Correct Execution (ACE) 分析。儘管這些減少方法是有效的，但它的運行
時間在分析過程中仍然很重要。
在這篇論文中，為了加速分析過程，我們將基於FPGA的仿真與降低錯誤方法相結合。
我們找出了基於ACE的方法中的兩個模擬的主要步驟，並在FPGA中實現，以加速該過
程。第一部分是提取出暫存器的讀寫狀態的無故障模擬。通過FPGA仿真，與軟體模擬的
提取過程相比，我們可以實現高達361倍的加速。第二部分是單週期錯誤模擬，它分析了
一個週期內的暫態錯誤影響，其中FPGA仿真平均加速了高達282倍。
在實驗中，我們使用RISC-V內核-PicoRV32進行的。在降低錯誤分析過程之後，剩
餘的錯誤可以減少到原本總錯誤數量的1.6%以下。通過整合所有軟體部分和FPGA仿真
過程，與純軟體的降低錯誤方法的流程相比，整體錯誤減少分析流程的速度平均提高
了109倍。在我們的案例中，端對端之錯誤降低方法可以在幾秒鐘內完成，而不是幾分
鐘。所提出的整合FPGA流程在加速暫態錯誤的長周期之模擬方面是實用的。

The chips with advanced process nodes are more sensitive to transient faults, so it’s essential to
perform functional fault simulation with transient faults to evaluate the vulnerability of the circuits.
However, the simulation is time-consuming because of the complexity of circuits and the large
number of transient faults. To improve the simulation efficiency, fault reduction methods are used
to prune out unnecessary faults in the process. The methods are often based on Architecturally
Correct Execution (ACE) analysis. Even though these reduction methods are effective, its run time
is again non-trivial in the analysis process.
In this thesis, in order to accelerate the analysis process, we integrate FPGA-based emulation
with the fault reduction method. Two major simulation blocks in the ACE-based methods are identified and implemented in FPGA to speedup the process. The first part is the fault free simulation
to trace read/write cycles of memory elements. With FPGA emulation, we can achieve up to 361X
speedup as compared with a software simulation tracer. The second part is the single-cycle fault
simulation which analyzes transient fault effects within one cycle, where up to 282X speedup is
also recorded with FPGA emulation scheme.
Our experiments are performed with a RISC-V core - PicoRV32. After the fault reduction
process, the remaining faults can be reduced to under 1.6% of total faults. With the inclusion of
all software components and FPGA emulation processes, the overall fault reduction analysis flow
has a average speedup of 109 times compared with a pure software implementation. The end-toend fault reduction can be done in a few seconds instead of minutes in our cases. The proposed
integrated FPGA flow is practical in speedup the long simulation efforts of transient faults.

Contents
1 Introduction 9
1.1 Objective and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Background and Related Work 11
2.1 ACE Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 ACE-PRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 FPGA Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Fault Reduction Method 16
3.1 Original Software Flow of Fault Reduction Analysis . . . . . . . . . . . . . . . . . 16
3.2 Extracting Read/Write Cycles and ACE Analysis . . . . . . . . . . . . . . . . . . 17
3.3 Single-Cycle Fault Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Graph Analysis of Equivalent and Masking Faults . . . . . . . . . . . . . . . . . . 18
4 FPGA Emulation System 20
4.1 Fault Free Emulation For Recording Read/Write Cycles of all Registers . . . . . . 20
4.1.1 Fault Free Emulation System Architecture . . . . . . . . . . . . . . . . . . 20
4.1.2 Fault Free Emulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Single-Cycle Fault Emulation System . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1 Single-Cycle Fault Emulation System Architecture . . . . . . . . . . . . . 24
4.2.2 Single-Cycle Fault Emulation Flow . . . . . . . . . . . . . . . . . . . . . 30
4.3 Complete Fault Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Complete Fault Emulation System Architecture . . . . . . . . . . . . . . . 31
4.3.2 Classification of Fault Effects . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.3 Complete Fault Emulation Flow . . . . . . . . . . . . . . . . . . . . . . . 33
5 Experimental Results 36
5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Fault Reduction Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Run Time Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1 Run Time of Fault Free Simulation/Emulation . . . . . . . . . . . . . . . . 38
5.3.2 Run Time of Single-Cycle Fault Simulation/Emulation . . . . . . . . . . . 40
5.3.3 Overall Run Time of The Fault Reduction Flow . . . . . . . . . . . . . . . 45
5.4 Complete Fault Emulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 Conclusions and Future Work 50

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