由於在半導體的製造中，產品的質量需要高度的可靠性，因此會生成更多的測試及檢測以保證準確地辨別晶片的優劣從而提高測試的品質。在這些測試中，我們傾向於發現哪些測試與最終結果之間的關係更有相關性。在這項工作中，我們提出了對於兩種機器學習方法進行修改，以判斷這些測試的重要性與晶片優劣的相關性以及改善測試的品質。
在機器學習中，要如何選取特徵是非常重要的一步，這是因為在大量的特徵數據與測試結果答案的關係不確定性。在大量的測試項目中，很多的測試項目可能是多餘的或是與最後晶片的質量並無太大的關聯性，其中只有少數測試項目足以區分特定產品的晶片質量。在這種情況下，我們傾向於找到與所需晶片分類有關的更重要的測試項目。
在本文中，我們的目標是找到一些可以使用機器學習工具大致預測好晶片和壞晶片之間結果的測試項目，從而減少測試項目的數量。本文實現了決策樹（DT）和隨機森林（RF）等機器學習方法。由於缺乏數據，我們還生成了具有延遲缺陷的數據，以觀察我們的方法捕獲到的重要特徵。

Since the quality of the silicon manufacturing needs high reliability, the test patterns are generated more to guarantee the category that the chips lie in. Among those tests, we tend to find which test patterns have tighter relationships with the final results. In this work, we modify two machine learning methods for identifying the importance of these test patterns with the quality of the chips.
In machine learning, feature selection is quite an important step due to the data set has uncertain relation to the labeled answer. The large amount of test items might be redundant and only few of them are enough to discriminate the quality of the chips for specific product. In this case, we tend to find the more important test items related to the classification for the required chips.
In this thesis, the goal is to find some test items that can roughly predict the results between good or bad chips by using machine learning tools, which can reduce the test items for production. Machine learning approach such as Decision Tree (DT) and Random Forest (RF) are implemented in this thesis. Due to the lack of data, we also generate data with delay defect to observe the important feature captured by this approach.

摘要 I
Abstract II
List of Contents III
List of Figures V
List of Tables VIII
Chapter 1. Introduction 1
1.1. Motivation 1
1.2. Typical Production Test Flow 5
1.3. Organization 6
Chapter 2. Decision Tree (DT) and Random Forest (RF) Classification 8
2.1. Problems of ML and Additional Techniques 8
2.1.1. Data Imbalance and Overfitting 8
2.1.2. Data Measurement Test 9
2.1.3. Finding Outliers as Failed Chips 11
2.2. Decision Tree (DT) 15
2.3. Random Forest (RF) 20
2.4. Proposed Enhanced DT and RF 23
A. Limiting Max_depth 24
B. Class Weight 25
C. Root Condition 27
Chapter 3. Generation of Data Used for Machine Learning Approach 31
3.1. Product Case Studies 31
3.1.1. ML Methods for Product Case I 32
A. Decision Tree (DT) 32
B. Random Forest (RF) 34
C. Methods for Avoiding Overfitting 35
D. Finding Important Features 39
3.1.2. ML Methods for Product Case II 43
A. Decision Tree (DT) 43
B. Random Forest (RF) 46
C. Important Features 47
3.2. Introduction to Small Delay Defects 48
3.3. Data Generation Flow 50
Chapter 4. Experimental Results 52
4.1. Experimental Case: Carry-Save Multiplier 52
4.2. Results of Decision Tree (DT) 56
4.3. Results of Random Forest (RF) 57
4.4. Influence of Important Feature 58
4.5. Different Dataset for Product Variation 61
Chapter 5. Conclusion and Future Work 67
5.1. Conclusion 67
5.2. Future Work 68

[1] R. Rajsuman, System-on-a-Chip Design and Test, Artech House Publishers, 2000.
[2] Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, VLSI test principles and architectures: design for testability, San Francisco: Elsevier (Morgan Kaufmann), 2006.
[3] Michael Bushnell and Vishwani Agrawal, "Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits," in Proc. Springer Science & Business Media, 2004.
[4] Miron Abramovici, Melvin A Breuer, and Arthur D Friedman, "Digital systems testing and testable design," in Proc. Computer science press New York, 1990.
[5] Michael L. Bushnell and Vishwani D. Agrawal, Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits, 2000.
[6] Baris Arslan and Alex Orailoglu, "CircularScan: A scan architecture for test cost reduction," in Proc. DATE, pp. 1290-1295, 2004.
[7] R. L. Wadsack, "Fault modeling and logic simulation of CMOS and MOS integrated circuits," The Bell System Technical Journal, vol. 57, no. 5, pp. 1449-1474, 1978.
[8] John A Waicukauski, Eric Lindbloom, Barry K Rosen, and Vijay S Iyengar, "Transition fault simulation," in Proc. IEEE Design & Test of Computers, vol. 4, no. 2, pp. 32-38, 1987.
[9] R. R. Schaller, ""Moore's law: past, present and future," in Proc. IEEE spectrum, vol. 34, no. 6, pp. 52-59, 1997.
[10] Matthias Sauer, Alexander Czutro, Ilia Polian and Bernd Becker, "Small-delay-fault ATPG with waveform accuracy," in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 30-36, 2012.
[11] Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha and Ruifeng Guo, "An experimental study of N-detect scan ATPG patterns on a processor," in Proc. 22nd IEEE VLSI Test Symposium, pp. 23-28, 2004.
[12] Sanjay Sengupta, Sandip Kundu, Sreejit Chakravarty, Praveen Parvathala, Rajesh Galivanche, George Kosonocky, Mike Rodgers, TM Mak, "Defect-based test: A key enabler for successful migration to structural test," Intel Technology Journal, 1999.
[13] H. H. Chen, "Beyond structural test, the rising need for system-level test," in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, 2018.
[14] Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, and Ananta Majhi, "Towards a world without test escapes: The use of volume diagnosis to improve test quality," in Proc. IEEE International Test Conference, pp. 1-10, 2008.
[15] Sounil Biswas and Bruce Cory, "An industrial study of system-level test," in Proc. IEEE Design & Test of Computers, vol. 29, no. 1, pp. 19-27, 2012.
[16] Sde-Paz, Shlomi, and Eyal Salomon, "Frequency and power correlation between at-speed scan and functional tests.," in in Proc. IEEE International Test Conference, 2008.
[17] Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang, "A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices," in Proc. IEEE International Test Conference in Asia (ITC-Asia), pp. 13-18, 2020.
[18] L. Wang, Support vector machines: theory and applications, Springer Science & Business Media, 2005.
[19] Mohammed J. Islam, Q. M. Jonathan Wu, Majid Ahmadi, and Maher A. Sid-Ahmed, "Investigating the Performance of Naive- Bayes Classifiers and K- Nearest Neighbor Classifiers," in Proc. International Conference on Convergence Information Technology (ICCIT), pp. 1541-1546, 2007.
[20] AnthonyJ.Myles,RobertN.Feudale,YangLiu,Nathaniel A. Woody and Steven D. Brown, "An introduction to decision tree modeling," Journal of Chemometrics: A Journal of the Chemometrics Society, pp. 275-285, 2004.
[21] M. Pal, "Random forest classifier for remote sensing classification," International journal of remote sensing, pp. 217-222, 2005.
[22] M. C. A. M. Koolen, J. A. M. Geelen and M. P. J. G. Versleijen, "An improved de-embedding technique for on-wafer high-frequency characterization," in Proc. Bipolar Circuits and Technology Meeting, pp. 188-191, 1991.
[23] Harry Chen, Roger Hsu, PaulYoung Yang., and J.J. Shyr, "Predicting system-level test and in-field customer failures using data mining," in Proc. IEEE International Test Conference (ITC), pp. 1-10, 2013.
[24] W. Robert Daasch and Robert Madge, "Data-driven models for statistical testing: measurements, estimates and residuals," in Proc. IEEE International Test Conference (ITC), 2005.
[25] Sagar S. Sabade and Duncan M. Walker, "IC outlier identification using multiple test metrics," in Proc. IEEE Design &Test of Computers, vol. 22, no. 6, pp. 586-595, 2005.
[26] P. M. O'Neill, "Statistical test: A new paradigm to improve test effectiveness &efficiency," in Proc. IEEE International Test Conference, 2007.
[27] P. M. O'Neill, "Production multivariate outlier detection using principal components," in Proc. IEEE International Test Conference (ITC), pp. 1-10, 2008.
[28] Ender Yilmaz, Sule Ozev, and Kenneth M. Butler, "Adaptive multidimensional outlier analysis for analog and mixed signal circuits," in Proc. IEEE International Test Conference (ITC), pp. 1-8, 2011.
[29] G. S. Maddala, Introduction to Econometrics (2nd ed.), MacMillan Publishing Company, p. 89.
[30] F. E. Grubbs, "Procedures for detecting outlying observations in samples," Technometrics, vol. 11, no. 1, pp. 1-21, 1969.
[31] Baker, Keith, and Jos Van Beers, "Shmoo plotting: The black art of IC testing.," in Proc. IEEE Design & Test of Computers, vol. 14, no. 3, pp. 90-97, 1997.
[32] Kun-Jin. Lin and Cheng-Wen Wu, "Easily Testable Cellular Array Multipliers," Journal of Information Science and Engineering, vol. 7, no. 3, pp. 367-383, 1991.
[33] Srivastava, N., Hinton, G., Krizhevsky, A., Sutskever, I., & Salakhutdinov, R., "Dropout: a simple way to prevent neural networks from overfitting," The journal of machine learning research, vol. 15, no. 1, pp. 1929-1958, 2014.