本論文描述一個應用於25 0C到1250C精準度為0.10C的溫度感測器上的二階三角積分調變器，透過TSMC 65製程實現電路，並且解析度達到有效位元14bit。首先，解釋SDM兩大特色:超取樣(Oversampling)和雜訊轉移(Noise Shaping)，接著定義每個子電路規格，並且選擇使用CIFB架構讓STF在頻帶外有更好的濾波效果；考慮NTF最佳化、動態範圍縮放避免積分器輸出飽和、NTF極點皆在z-domain維持電路穩定，可以定義出整體SDM係數意即整個SDM的STF和NTF。
因為溫度變化頻率較低意即SDM輸入端為一個較低頻的訊號，所以調變器除了會受到熱雜訊影響還會看到很大的閃爍雜訊；再加上製成變異造成元件不匹配而在輸入端產生偏差電壓，此電壓可視為低頻雜訊；因此在兩級積分器上加入Chopper技術先把訊號移到高頻和低頻雜訊分離，再將訊號移到原本頻帶同時將低頻雜訊移到fc處，透過低通濾波器濾除高頻雜訊，此做法可以減少頻帶內偏差電壓以及低頻的閃爍雜訊1/f達到提升SNR的效果。
最後在供電電壓為1.2V、訊號頻寬為20KHz、超取樣率為256倍意即取樣頻率10M的情形下，所設計的二階調變器可以達到SNR為92.97 dB，相當於有效位元數15.1位元。

This thesis describes a second-order delta-sigma modulator with a 14 significant bits. It is applied to a smart temperature sensor that is accurate to within +0.10C over the temperature range of 25 0C to 125 0C, and to be implemented with TSMC 65 process.

The two major features of SDM, oversampling and noise shaping, will be introduced, and then the specifications of each sub-circuit will be defined. The CIFB architecture will be chosen to make the STF have a better filtering performance.

To consider the optimization of NTF and the using of dynamic range scaling to avoid the output of integrator saturated, all of the poles of NTF should be kept stable in the Z-domain. And then all of the coefficients will be defined, that means the STF, NTF of SDM will be defined.

Since the frequency of variation of temperature is low that means the input of SDM is a low frequency signal, the modulator will be impacted not only by the thermal noise also by the flicker noise, and the mismatch of process variation will caused the biasing voltage that could be considered as a low frequency noise at the input of SDM. As a result, by adding a chopper technique on the second-order modulator to transfer the signal to a higher frequency band that will separate the signal from the low frequency noise. and then transfer the signal back again to the original band and at the same time transfer the low frequency noise to the fc band, and use the low pass filter to filter the high frequency noise. The chopper can reduce the biasing voltage and the low-frequency flicker noise 1/f to get the higher SNR
.
In the situation of power supply voltage 1.2V, signal bandwidth 20 KHz,
the oversampling ratio is 256 that means sampling frequency is 10 MHz,
the designed modulator achieves 98.25 dB SNR which equals 16.03 significant valid bits.

中文摘要 I
英文摘要 II
目錄 III
圖目錄 VI
表目錄 Ⅸ
第一章 序論 1
1.1研究動機 1
1.2論文章節組織 1
第二章 三角積分類比數位轉換器原理簡介 2
2.1類比數位轉換器分類 2
2.2量化器雜訊，線性量化器模型 2
2.3尼奎斯(NYQUIST)定律V.S. 超取樣 4
2.3.1 尼奎斯定律 4
2.3.2 超取樣原理 4
2.3.3比較尼奎斯定律和超取樣原理對量化雜訊的影響 5
2.4雜訊整形原理(NOISE SHAPING) 6
2.5穩定度 8
第三章 各子電路系統架構選定及分析模擬 10
3.1選定子電路規格 10
3.2調變器架構選取 10
3.2.1單迴路串接積分器前饋型(CIFF) 10
3.2.2單迴路串接積分器回授形(CIFB) 11
3.2.3架構選擇 12
3.3係數選擇 12
3.4不同地方的雜訊對三角積分調變器的影響 16
3.5交換電容積分器 18
3.5.1交換式電容積分器操作原理 18
3.5.2交換式電容積分器的雜訊分析 19
3.5.3交換式電容積分器之取樣電容選擇 22
3.5.4有限的直流增益及頻寬對積分器的影響 23
3.5.4¬_1有限直流增益 23
3.5.4_2有限頻寬 26
3.5.5取樣開關 27
3.5.5¬_1通道電荷注入效應 28
3.5.5¬_2時脈饋入效應 29
3.5.5_3導通電阻非線性 29
改善¬_1互補式開關 31
改善¬_2模仿(dummy)元件 32
改善_3下版取樣 32
第四章 電路的實現 36
4.1 OP架構的選擇及模擬 36
4.1.1頻率補償 37
4.1.2 constant gm 37
4.2取樣開關 39
4.3斬波器(CHOPPER) 40
4.3.1相關雙取樣積分器(CDS) 40
4.3.2 斬波器 41
4.4時脈產生電路 44
4.5量化器的架構 45
4.6栓鎖器 47
4.7一位元DAC 48
4.8整體三角積分類比數位轉換器 49
第五章 SDM的應用 51
5.1溫度感測器系統介紹 51
5.2雙載子接面電晶體和溫度的關係 52
5.3帶差參考電路(BANDGAP)原理 54
5.4 BANDGAP最後架構及模擬 56
附錄A
A.1 訊號雜訊比(SNR) 59
A.2 訊號雜訊諧波比(SNDR) 59
A.3 有效位元(ENOB) 59
A.4 過載準位(OL) 60
參考文獻 61

[1] I. Ahmed, Pipelined ADC Design and Enhancement Techniques. Springer, 2010.
[2] Rocío Río Fernández, Fernando Medeiro Hidalgo, Belén Pérez Verdú, and José Manuel Rosa Utrera, CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom. Springer, 2006.
[3] F. Gerfers, and M. Ortmanns, Continuous-Time Sigma-Delta A/D Conversion. Springer 2006.
[4] Oppenheim and Willsky, Signals and Systems. 2nd Edition, Prentice Hall, 1997.
[5] P. E. Allen, CMOS Analog Circuit Design. New York:Oxford,2002
[6] J. H. Fischer, “Noise sources and calculation techniques for switched capacitor filters,” IEEE J. Solid-State Circuits, vol. SSC-17, no. 4, pp. 742–752, Aug. 1982.
[7] K. Kundert, Simulating Switched-Capacitor Filters with SpectreRF. , 2006. [Online]. Available: http://www.designers-guide.org/analysis [8] R. Schreier, J. Silva, J. Steensgaard, and G. Temes, “Design-oriented estimation of thermal noise in switched-capacitor circuits,” IEEETrans. Circuits Syst. I: Reg.Papers, vol. 52, pp. 2358–2368, Nov. 2005.
[9] 吳介琮,資料轉換積體電路. 2014.
[10] C. Enz E. Vittoz F. Krummenacher "A CMOS chopper amplifier" IEEE J. Solid-State Circuit vol. 22 no. 3 pp. 335-342 1987.
[11] K. Hsieh and P. Gray, "A low-noise chopper-stabilized differential switched-capacitor filtering technique," 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, New York, NY, USA, 1981, pp. 128-129.
[12] A.Yubawa, “A CMOS 8-bit High-Speed A/D Converter” IEEE J. of Solid-State Circuits, Vol 20, no. 3, pp. 775-779, June 1985.
[13] Yan Huang, H.Schleifer, and D.Killat, “Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs” Circuit Theory and Design (ECCTD), Sept. 2013.
[14] L. Yao, M. Steyaert, and W. Sansen, “A 1-V 140- W 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809 -1818, Nov. 2004.
[15]M. A. P. Pertijs, K. A. A. Makinwa and J. H. Huijsing, "A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.1/spl deg/C from -55/spl deg/C to 125/spl deg/C," in IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2805-2815, Dec. 2005.
[16]B.Razavi,Designed of analog CMOS Inregrated Circuit,McGraw-Hill,2003
[17]G.C.M. Meijer, Integrated Circuits and Components for Bandgap References and Temperature Transducers, PhD thesis, 1982.
[18] http://www.mathworks.com/matlabcentral/fileexchange/19-delta-sigma-toolbox
[19] W. H. Ki and G. C. Temes, ”Offset-compensated switched-capacitor integrators,”
Proc. IEEE Int. Symp. Circuits and Systems, pp.2829 -2832, May.1990.