隨著通訊技術日新月異的進步與發展，資料傳輸量越來越大，因此在數位類比轉換器與類比數位轉換器的需求也相對的重要，而在數位類比轉換器中，又以高速、高線性度的電流引導式數位類比轉換器最被廣泛的使用。電流引導式數位類比轉換器挾著可以在高速高頻寬的操作環境下達到高動態規格之優勢，成為現今通訊系統中的主流，因此面積控制就顯得更加重要。

本文主旨在實現一個具動態元件匹配的電流引導式數位類比轉換器，為了達到高SFDR規格要解決在電路實作上諸多非理想的效應，電流源的不匹配、電流源開關在切換時產生的glitch、電流源的有限阻抗及寄生電容等等…，這些都是造成動態規格減低的重要議題。為了減少mismatch的影響，除了增加電流源的大小之外，我選擇用另外一種”動態元件匹配”方法，雖然增加noise floor 的高度，但同時也會降低third harmonic的高度，可以得到比較好的動態規格。

在晶片的實現上，本論文實現了一個十位元具動態元件匹配之電流引導式數位類比轉換器，採用製程為TSMC 65 nm，1P9M互補金氧半導體，偏壓電路以及電流源供應電壓為2.5V，其餘部分則為1.2V，雙端差動輸出為0.2V，輸入訊號頻率為40MHz，取樣頻率為4GHz之下，透過RRUS DEM的技巧以及在佈局上面的特殊走線方法，能將動態規格SFDR從65dB提升到69dB。

With the rapid development of communication systems, data of the digital transmission is growing larger. Therefore, the demand of digital-to-analog data converter plays an important role in recent year. One of them is Current Steering Digital to Analog Converter which is widely used with high-speed, high-linearity characteristic. Current Steering DAC can reach great dynamic performance under high bandwidth environment, become the most popular architecture nowadays. The layout area control of DAC is also important.

This thesis is implementing a Current Steering DAC with dynamic element matching techniques. In order to achieve high SFDR performance, we need to solve many non-ideal effect, such as current source mismatch, induced glitch when switch transient, current source finite impedance and parasitic capacitor etc. The above mentioned are all critical issue when designing a high quality DAC. In order to reduce the impact of current source mismatch, we not only increase the size of MOSFET, also introduce a method called “Dynamic Element Matching”. Although this method increases the noise floor in the spectrum diagram, it can lower the third harmonic tone, achieving outstanding dynamic performance.

In the realization of this chip, a 10-Bit 4-GS/s Current-Steering DAC with dynamic element matching techniques is implemented in TSMC 65nm. The power supply for current source and bias circuit is 2.5V and others are 1.2V with differential output Vpp=0.2V. Through the RRUS DEM techniques and special routing skills, SFDR can be improved from 65dB to 69dB with input frequency=40M/s and sampling frequency=4G/s.

第1章 序論…………………………………………………………….1
第2章 電流引導式數位類比轉換器基本原理……………………….3
第3章 電流引導式數位類比轉換器設計考量與提高規格之技巧…...25
第4章 電路實現…………………………………………………………44
第5章 模擬結果與布局量測規畫…………………………………….....58
第6章 結論………………………………………………………………75
參考文獻…………………………………………………………77

[1] Wei-Hsin Tseng, “High-Speed Current-Steering Digital-to-Analog Converters”, A Dissertation for the Degree of Doctor of Philosophy in Electronics Engineering of National Chiao-Tung University,2011
[2] L.R. Carley, “ A noise shaping Coder Topology for 15+ bit Converters”, IEEE journal of solid state circuits, April 1989
[3] Wei-Te Lin and Tai-Haur Kuo, “A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection,” IEEE JSSC, 2012.
[4] Xin-Hao Wang, “1-V 10-bit 2GSample/s D/A Converter based on Precision Current Reference in 90-nm CMOS.” A thesis for the Degree of Master of Science in Electronics Engineering of National Central University,2008
[5] A. Van den Bosch, M. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters", Proc. IEEE Int. Conf. Electronics, Circuits and Systems, 1999
[6] Bugeja, Alex R., Song, Bang-Sup, Rakers, Patrick L. and Gillig, Steven F., “A 14-b, 100-MS/s CMOS DAC designed for spectral performance.” IEEE Journal of Solid-State Circuits, 1999
[7] H. C. Yang, T. S. Fiez, and D. J. Allstot, “Current-feedthrough effects and cancellation techniques in switched-current circuits,” in Proc. IEEE International Symposium on Circuits and Systems, 1990
[8] G. Liu and L. He and X. Xue and Q. Shi, "A new current switch driver with improved dynamic performance used for 500MS/s, 12-bit Nyquist current-steering DAC", 2011
[9] K. O’Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, “A 12-bit 320-MSample/s Current Steering CMOS D/A Converter in 0.44 mm2,” IEEE J.Solid-State Circuits, 2004.
[10] A. Van den Bosch et al., “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A
converter,” IEEE J. Solid-State Circuits, 2001
[11] Wei-Te Lin and Tai-Haur Kuo, "A 12b 1.6GS/s 40mW DAC in 40nm CMOS with > 70dB SFDR over entire Nyquist bandwidth" 2013
[12] TSMC Confidential Information 782037 GLOBAL UNICHIP CORP,2010
[13] Pelgrom J.M., Duinmaijer C.J., Welbers P.G., “Matching properties of MOS transistors,” IEEE J Solid-State Circuits, 1989
[14] Chi-Hung Lin and K. Bult, “A 10-b, 500-Msample/s CMOS DAC in 0.6 mm,” IEEE J. Solid-State Circuits, 1998
[15] Yi-An Chao, “A 12-bit 100MHz DAC with Dynamic Element Matching and Output Impedance Calibration”, A Dissertation for the Degree of Master science in NCKU, 2011
[16] Wei-Te Lin, “Dynamic-Performance-Improved Techniques for Nyquist-Rate Current-Steering DACs”, A Dissertation for the Degree of Doctor of Philosophy in Electronics Engineering of National Cheng Kung University,2013
[17] Jurgen Deveugele, Geert Van der Plas, Michiel Steyaert, and Willy Sancen, “ A Gradient Error and Edge Effect Tolerant Switching Scheme for a High Accuracy DAC ”, Circuits and Systems I, Regular Papers, IEEE Transactions on, VOL. 51, NO. 1, January 2004, pp. 191-195
[18] Van der Plas, G.A.M, et al, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC”, IEEE Journal of Solid-State Circuits, vol. 34, No. 12, Dec. 1999
[19] Hiroshi Takakura, Masashige Yokoyama and Akira Yamaguchi, “A 10 bit 80MHz Glitchless CMOS D/A Converter,” in Proc. IEEE CICC, 1991
[20] Bastos J, Marques A M, Steyaert M S J, et al 1998 A 12-bit intrinsic accuracy high-speed CMOS DAC IEEE J. Solid-State Circuits