隨著深度類神經網路與人工智慧的崛起，在行動裝置上實現高速運算及低功耗成為主要的需求，因此邊緣運算應運而生，由於其可利用訓練好的模型在特定排程或時間內完成推論，不同於訓練時所需的巨量運算，能夠減少大量的運算量，而後出現了記憶體內運算(Computing-In-Memory)、近記憶體運算(Near-Memory-Computing)以及記憶體處理器(Processor-In-Memory)等新的概念，透過減少資料搬運過程中消耗的巨大能量，並且同時擁有記憶與運算的功能，記憶體內運算扮演深度類神經網路處理器中硬體加速器的角色。

本篇論文提出一個循序漸近式參考電流產生器，應用在非揮發性記憶體內運算巨集進行乘法與累加運算後實現高輸出精度，同時具有高能源效率且節省面積的優點。透過台積電55奈米CMOS邏輯製程，本篇論文在一個 2Mb電阻式記憶體內運算巨集的6位元及8位元輸出下分別提高了1.38及7.02倍的功績。

With the rapid development of deep neural network (DNN) and artificial intelligence (AI),
mobile devices require high operation speed and low power consumption. Edge computing comes out to meet the requirement since it can use a trained model to complete inference in a specific schedule or time, different from the huge amount of operations required for training. Therefore, some new concepts have emerged such as Computing-In-Memory (CIM), Near-Memory-Computing (NMC) and Processing-In-Memory (PIM). By reducing energy consumption of the data movement, and implementing computations inside memory, CIM become an AI accelerator for DNN processor.

To support high output precision for MAC operations in non-volatile computing-in-memory macro, we propose a Successive Approximation Reference Current Generator (SARCG) which can realize energy-efficiency and area reduction in high output precision. The proposed scheme in a 2Mb ReRAM CIM macro fabricated in TSMC 55nm CMOS logic process achieves 1.38x and 7.02x improvement in figure of merit (FoM) for 6bit and 8bit output respectively.

Contents
摘要...i
Abstract...ii
致謝...iii
Contents...iv
List of Figures...vi
List of Tables...vii
Chapter 1 Introduction...1
1.1 Memory Landscape...1
1.2 von Neumann Bottleneck...4
1.3 Computing-In-Memory (CIM)...5
Chapter 2 Characteristic of Contact-ReRAM...7
2.1 Structure of Contact-ReRAM...7
2.2 Switching Mechanisms...8
2.3 Write Operations...9
2.4 Read Operation...10
Chapter 3 Previous Work...11
3.1 The role of Reference generator in CIM structure...11
3.2 Previous works...11
3.2.1 Input-Aware dynamic IREF generation (IA-REF)...11
3.2.2 Global-VREF-GEN & Local-IREF-SEL scheme...13
Chapter 4 Proposed Circuit Scheme and Analysis...17
4.1 Proposed Successive Approximation Reference Current Generator (SARCG)...17
4.1.1 Motivation and Concept...17
4.1.2 Structure of Proposed SARCG Scheme...20
4.1.3 Operations of Proposed Scheme...21
4.2 Analysis and Comparison...27
4.2.1 Power...27
4.2.2 Area...30
4.2.3 Figure of Merit (FoM)...32
4.3 Summary...33
Chapter 5 Measurement Results and Conclusion...34
5.1 Floor Plan of ReRAM CIM Macro...34
5.2 Design for Test-chip...35
5.3 Measurement results...35
5.4 Conclusions and Future Work...37
Reference...39

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