在現今的車用元件設計中，通常需要透過線上安全檢查才能確保達到高度車輛安全完整性等級(Automotive Safety Integrity Level)。身為本論文的標靶電路，對延遲鎖向迴路電路而言，最重要的安全性指標為：當延遲鎖向迴路電路完成鎖定階段後，〝輸入時間訊號及輸出時間訊號兩者之間的相位誤差〞。在本論文中，我們提出了一個相位差監測系統可以對於延遲鎖向迴路電路的輸入時間訊號及輸出時間訊號兩者之間的相位誤差進行監測，且此系統電路僅使用標準元件所組成實現。我們提出的這個監測系統，可以連續性的監測輸入時間訊號及輸出時間訊號兩者之間的相位誤差，並且在指定的監測周期內記錄下最差情況的相位誤差值。監測結果會顯示出危險的相位誤差值，並且可以發出一個安全性危險警報。我們將此監測系統加到一個延遲鎖向迴路電路上進行實驗，實驗在90奈米製程下進行佈局後模擬，來驗證此監測系統的有效性。實驗模擬結果顯示，此監測系統可以發現在一奈秒內發生的動態功率故障而引起的危險相位誤差。

In today’s automotive ICs, online safety checking is often required in order to achieve a high Automotive Safety Integrity Level (ASIL). For a Delay-Locked Loop (DLL) as the target in this work, the most important safety (or health) indicator is the “phase error between the input clock signal and the output clock signal”. In this paper, we present a phase error monitoring scheme for DLLs, using circuits made of only standard cells. The proposed scheme can monitor the phase error continuously to record its worst-case phase error values during a designated monitoring session. As a result, hazardous phase error glitches can be exposed and a safety hazard alarm can be raised. We have added this monitoring scheme to a Delay Lock Loop to do the implementation in a 90nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that it can help discover hazards induced by dynamic power glitches that occurs within 1ns.

Abstract...........................................................i
摘要..............................................................ii
誌謝.............................................................iii
Content...........................................................iv
List of Figures....................................................v
List of Tables....................................................vi
Chapter 1 Introduction.............................................1
1.1 Introduction...................................................1
1.2 Thesis Organization............................................4
Chapter 2 Preliminaries............................................5
2.1 Architecture and Operations of Delay-Locked Loop...............5
2.2 Performance Specifications of a Delay-Locked Loop..............9
Chapter 3 Proposed Monitoring Scheme for DLL......................11
3.1 Architecture and Function.....................................11
3-2 Vernier Delay Line Pair – Micro-architecture and Circuits.....16
3-3 Worst-Case PE Recorder Circuit................................22
3-4 Thermometer-to-Binary Encoders................................26
Chapter 4 Simulation Results......................................27
4.1 Post-Layout Simulation........................................27
4.2 Histogram of Phase Errors Samples.............................29
4.3 Detection of Power Glitches Induced Safety Hazard.............31
4.4 The Influence of Phase Detector...............................38
Chapter 5 Conclusion..............................................40
References........................................................42

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