有許多具有安全意識的移動設備，使用安全散列算法（SHA）或進階加密標準（AES）功能進行數據加密，通常需要較短的讀取時間（TAC）和搭配wide-IO的非揮發性記憶體（NVM）以實現高讀取帶寬功能。自旋力矩轉移-磁阻式隨機存取記憶體（STT-MRAM）是主要用於先進製程節點的on-chip非揮發性記憶體。但是，它需要具備小偏移量的感測放大器才能在較小的穿隧式磁阻比例(TMR-Ratio)進行穩定的讀取，因此需要以大量的面積消耗和讀取能量（ERD）作為代價。設計一個安全相關的自旋力矩轉移-磁阻式隨機存取記憶體巨集主要面臨兩個挑戰：
1. 使用大量數目的感測放大器進行平行wide-IO讀取可實現較短的讀取時間，但會導致峰值電流（IPEAK）提高和大量面積消耗。若使用較少數目的感測放大器進行序列的Wide-IO讀取可減少高峰值電流和面積消耗，但會導致較長的讀取時間且較低的讀取帶寬。
2. 具有較高峰值電流的自旋力矩轉移-磁阻式隨機存取記憶體巨集會降低晶片的電源穩定性，可能會導致同一晶片上對雜訊敏感的區塊出現故障。
本文主要討論自旋力矩轉移-磁阻式隨機存取記憶體在高帶寬讀取中的出現的問題，並提出了一種多位元電流感測放大器（MB-CSA），該放大器具有電流欲度增強、製程變異容忍、小面積、低峰值電流、低能耗的特性，解決了在前面自旋力矩轉移-磁阻式隨機存取記憶體高帶寬巨集中提到的問題。
在台積電22 奈米製程分析下，我們提出的讀取架構相較於傳統電流感測放大器可多容忍70%的穿隧式磁阻比例。此外，減少的參考電流數量使多位元電流感測放大器的功耗相較於傳統電流感測放大器降低了53.3％，峰值電流降低了43.8％，而僅付出22.2％讀取速度的代價，與傳統電流感測放大器(並行感測)相比，在1024個輸出位元中每位元消耗的能量降低了43％。
最後，在台積電22奈米 CMOS工藝中製造的1Mb 自旋力矩轉移-磁阻式隨機存取記憶體巨集中驗證了我們提出的方案，本文的1Mb巨集在VDD = 0.85伏特時，讀取速度 = 2.75奈秒(ns)，在所有已發表的非揮發性記憶體中，該晶片的讀取帶寬為最高值(42.67GB/s)和最低讀取能量（0.23pJ/b），最大輸出位元為1024比特。

Many security-aware mobile devices, using Secure Hash Algorithm (SHA) or Advanced Encryption Standard (AES) functions for data encryption, require short read access time (TAC) and wide-IO from nonvolatile memory (NVM) for high read bandwidth function. Spin Torque Transfer- Magnetoresistive Random Access Memory (STT-MRAM) is the major on-chip NVM for advanced process nodes; however, it requires small-offset sense amplifiers (SAs) for robust read against small TMR-ratio at the expense of large area overhead and read-energy (ERD). Designing STT-MRAM macros for security-related applications imposes two main challenges:
1. Using a large number of SAs for parallel wide-IO readout achieves short TAC, but results in high peak current (IPEAK) and large area overhead. Using fewer SAs for sequential wide-IO readout reduces IPEAK and area overhead, but imposes long TAC and low read-bandwidth (BWR);
2. MRAM macros with high IPEAK degrade the supply (VDD) integrity of the chip, often leading to failure in noise-sensitive blocks on the same chip;
In this thesis, we discuss the issues in high bandwidth reading especially with STT-MRAM, and proposed a Multi-bit current sense amplifier (MB-CSA), which is featured with margin enhancement, offset suppression, small area, low peak current, and low energy consumption capability to solve the problems mentioned before in STT-MRAM high bandwidth macro.
Under tsmc 22 nm technology analysis, our proposed work achieves >70% lower tolerance on TMR-ratio than conventional sensing scheme. Moreover, the reduced number of IREF allows for an MB-CSA with 53.3% reduction in power consumption and 43.8% reduction in peak current with TAC overhead of only 22.2%, resulting in a 43% energy/bit reduction, compared to conventional read schemes (parallel sensing) for 1024b-IO.
Finally, our proposed scheme is verified in a 1Mb STT-MRAM macro fabricated in TSMC 22nm CMOS process, the proposed 1Mb macro demonstrated the largest number of data-out operations (DOUT=1024b) with TAC=2.75ns at VDD=0.85V, this device outperformed all reported NVM macros in terms of BWR (42.67GB/s) and ERD (0.23pJ/b).

致謝 ii
摘要 iii
Abstract v
Contents vii
List of Figures ix
List of Tables xi
Chapter 1 Introduction 1
1.1 The Role of Memory in SoC products 1
1.2 Memory Hierarchy 2
1.3 Challenges of Flash Memory 5
1.4 Emerging Non-Volatile Memories 8
Chapter 2 Characteristic of STT-MRAM 12
2.1 Introduction of MRAM 12
2.2 Read and Write Operations of STT-MRAM 14
2.3 Recent Development of STT-MRAM 17
Chapter 3 Design Challenges of STT-MRAM 21
3.1 Design Challenges 21
3.1.1 Threshold Voltage in Process 21
3.1.2 Issues of STT-MRAM 23
3.2 Structures and Operations of Conventional Sensing Schemes 24
3.3 Previous Small Offset Current Sense Amplifiers 26
3.4 Application of High Bandwidth Combined with NMC 32
Chapter 4 Proposed Circuits and Analysis 33
4.1 Motivation and Concept of Proposed Read Scheme 33
4.1.1 Pre-precharge and Sequential Sensing 35
4.1.2 Structure of Proposed MB-CSA 37
4.1.3 Operations of Proposed Sense Amplifier 38
4.2 Analyses and Comparison 50
4.2.1 Tolerance of Low TMR-Ratio and Sensing Yield 50
4.2.2 CSA Performance Comparison 53
4.2.3 Read Access Time Analyses 54
4.2.4 Comparison Table of Recent CSAs 55
4.2.5 Macro Level Read Bandwidth Analysis 56
Chapter 5 Measurement Result and Conclusion 57
5.1 STT-MRAM Macro Implementation 57
5.2 Design for Test 58
5.3 Measurement results 61
5.4 Conclusions and Future Work 65
Reference 67

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