在半導體製造產業中，要驗證一個已經設計好的電路是否有瑕疵需要實際等到晶片經過製程後再用掃描式電子顯微鏡(SEM)拍攝分析，這個過程需要耗費許多時間和金錢成本，所以發展出一套能夠基於給定的製程參數並預測出晶片實際經過對應製程蝕刻後結果的虛擬量測工具是非常必要的。現有的光學蝕刻模擬因為計算複雜度很高，因此所耗費的時間非常久，而本篇論文同樣是針對光學蝕刻模擬，期望能夠達到與現有光學蝕刻模擬器同樣準確度並同時加快模擬速度。
在本篇論文中我們提出了一個基於深度學習的網路用來模擬實際製程，藉由學習電路圖與SEM影像之間形狀的變形關係，最後產生出一張合成的SEM影像，藉此來提供虛擬量測及分析。除此之外，我們也藉由加入製程參數來模擬不同的製程環境下會對蝕刻結果產生的影響。
在ㄧ般情況下，ㄧ個電路圖在實際經過製程後的結果會因為曝光、化學反應及物理特性的影響下，使得結果無法跟原本預期的電路圖一模一樣。因此我們藉由前面已經訓練好的光學蝕刻模擬網路並額外加入ㄧ個影像生成網路，希望此網路可以學習如何修改原始電路圖並得到ㄧ個新的遮罩，使得此遮罩經過實際製程後能夠得到與原始電路圖相近的結果，以達到非監督式遮罩優化的目的。
最後我們藉由測試在許多不同基準的電路圖並與先前的方法做比較後計算出準確度，證實了我們方法的有效性和穩健性。

In semiconductor manufacturing, we cannot identify whether an already designed IC layout have defects until capturing and analyzing the scanning electron microscope (SEM) images of metal layers after a wafer fabrication process, making the IC layout verification very costly and time-consuming. Thus it is essential in semiconductor manufacturing to develop virtual metrology tools that can predict the properties of a wafer based on fabrication configurations. Existing physics-based lithography simulation schemes are very time-consuming because its high computational complexity. This thesis focuses on data-driven lithography simulation and desire to achieve the same accuracy as existing lithography simulators while speeding up the time of simulation.
In this thesis we first propose a convolutional neural network called LithoNet that mimics the manufacturing procedure to generate a synthetic image for virtual metrology. By learning the shape correspondence between the layout image and the corresponding SEM image, the proposed network can synthesize a SEM-styled image given an input layout. In addition, we use the wafer fabrication parameters to condition the generator so as to model the parametric product variation that can be inspected on the SEM images.
Moreover, existing lithography simulation algorithms used for suggesting a correction on a lithographic photomask according to a given layout by checking whether the shape of a fabricated IC circuitry matches exactly the layout design, is computationally very expensive. Thus, we propose an OPCNet, cooperating with a pre-trained LithoNet, to mimic the OPC (optical proximity correction) procedure used to correct the layout design and generate a photomask.
We evaluate our method using various benchmark layout patterns and compare with some existing method. The experimental results demonstrate the effectiveness and robustness of the proposed method.

摘 要 i
Abstract ii
Content iii
Chapter 1 Introduction 5
1.1 Research Background 5
1.2 Motivation 6
1.3 Contribution 9
Chapter 2 Related Work 11
2.1 Virtual Metrology 11
2.2 Lithography Simulation 12
2.3 Mask Optimization 13
Chapter 3 Proposed Method 14
3.1 Lithography Network 14
3.1.1 Overview of Architecture 14
3.1.2 Step I: Image Domain Transfer 15
3.1.3 Step II: Shape Deformation Estimation 16
3.1.4 Loss Functions for Training 17
3.2 Optical Proximity Correction Network 19
3.2.1 Architecture of OPCNet 19
3.2.2 Loss Functions for Training 20
Chapter 4 Experiments and Discussions 22
4.1 Lithography Network 22
4.1.1 Dataset 22
4.1.2 Metrics 22
4.1.3 Evaluation of LithoNet 23
4.2 Optical Proximity Correction Network 32
4.2.1 Dataset 32
4.2.2 Comparison among Different Loss Functions 32
4.2.3 Mask Prediction Results 33
Chapter 5 Conclusion 35
References 36

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