在背接式轉換器中，共模電壓是重要的議題之一。背接式轉換器由兩台轉換器組成，包含整流器以及逆變器。從克希荷夫電壓定律推導，背接式轉換器中的共模電壓為兩台轉換器之間各自的共模電壓差值。因此，以前的研究有提出主動式零向量調變策略，藉由減少各自的共模電壓而抑制整體系統的共模電壓大小。
本論文除了實現傳統抑制共模電壓的方法外，針對二階背接式轉換器，提出一種新的脈衝寬度調變策略，能完全消除共模電壓以及漏電流。同時，探討零序注入技術以及線性調變比的關係。當兩台電壓命令有相位差的狀況下，而衍生的過調變比狀況。因此，本論文提出新的直流鏈電壓權重控制來解決此現象。最後將此技術驗證於實驗平台上。

Common-mode voltage (CMV) is one of the most important issues for the back-to-back (BTB) converter. The BTB converter is consisting of two converters, the rectifier and the inverter. According to the derivation of Kirchhoff voltage law, the system CMV mainly depends on the CMV difference between the rectifier and the inverter. Therefore, some previous research has proposed Active zero state pulse width modulation, which can reduce the total CMV by decreasing the CMV at each converter.
This thesis not only testify the AZSPWM, but also presents a new PWM strategy for the BTB converter, which can cancel magnitude of common-mode voltage (CMV) and leakage current. Besides, we also discuss the relationship between zero-sequence-injection (ZSI) techniques and linear modulation index. In addition, discussing the phase difference between the rectifier and the inverter voltage commands, which may lead to the over-modulation problem. Therefore, this thesis will also present a new weighting DC bus voltage control to reduce the risk of the over-modulation. Finally, proposed control method will be validated by experimental results.

摘要.............................................................I
Abstract........................................................II
致謝............................................................III
List of Contents................................................IV
List of Figures.................................................VI
List of Tables...................................................X
CHAPTER 1 Introduction...........................................1
1.1 Motivation................................................1
1.2 Outline of the Contents...................................2
CHAPTER 2 Literature Review......................................3
2.1 Introduction.................................................3
2.1.1 Sine PWM / Space Vector PWM................................4
2.1.2 Active Zero State PWM......................................7
2.2 Common-Mode Component Analysis...............................8
CHAPTER 3 Operation Principal...................................12
3.1 Introduction................................................12
3.2 Control Block Diagram.......................................12
3.2.1 DC Bus Voltage Control....................................13
3.2.2 The d-q Synchronous Frame Model...........................14
3.3 Common-Mode Component Analysis of the two-level Back-to-Back Converter.......................................................19
3.4 Cyclic PWM for the Cancellation of Common-Mode Component....24
3.4.1 Displacement-pattern Modulation...........................25
3.4.2 Cyclic PWM Sequencing.....................................25
3.4.2 Ideal (Neglect the Dead-time) Realization in Cyclic PWM...33
3.4.3 Dead-Time Realization in Cyclic PWM.......................35
3.4.4 Dead-Time Compensation Realization in Cyclic PWM..........39
3.5 Zero-Sequence Injection for the two-level Back-to-Back Converter.......................................................44
3.6 Asynchronism Issue in the two-level Back-to-Back Converter..47
3.6.1 Limitation of Linear Modulation...........................48
3.6.2 Discussion of Control Freedom.............................50
3.7 Weighting DC Bus Voltage Control............................52
CHAPTER 4 Laboratory Test Results...............................54
4.1 Introduction................................................54
4.2 Experimental Results........................................55
4.2.1 Output Voltage and Output Current of the Inverter Side....56
4.2.2 Common-Mode Voltage and Leakage Current without ZSI.......59
4.2.3 Flux Ripple Analysis......................................66
4.2.4 Relationship between ZSI and the Leakage Current..........75
4.2.4 Test Results of Weighting DC Bus Voltage Control..........78
CHAPTER 5 Conclusions...........................................81
Appendix: System Overview.......................................82
Reference.......................................................83

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