帳號:guest(3.143.205.64)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):陳姵臻
作者(外文):Chen, Pei-Chen
論文名稱(中文):預測半導體產業晶圓疊對誤差補償之研究
論文名稱(外文):A Study on Compensation on Wafer Overlay Map Prediction in Semiconductor Manufacturing
指導教授(中文):廖崇碩
指導教授(外文):Liao, Chung-Shou
口試委員(中文):謝孫源
彭勝龍
口試委員(外文):Hsieh, Sun-Yuan
Peng, Sheng-Lung
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工業工程與工程管理學系
學號:106034530
出版年(民國):108
畢業學年度:107
語文別:中文
論文頁數:37
中文關鍵詞:疊對誤差預測圖像化分群相似度比對
外文關鍵詞:Overlay errorsPredictionVisualizationClusteringSimilarity Comparison
相關次數:
  • 推薦推薦:0
  • 點閱點閱:193
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
微影疊對誤差為晶圓層與層間曝光所產生的偏移,誤差需控制在規定的閥值內以確保晶圓的良率。疊對誤差的補償是透過機台的參數修正降低對後層曝光的影響,然而每一批晶圓都需量測決定補償的參數是很耗費時間與成本的,因此本篇論文著重在預測最佳補償參數以修正疊對誤差,期望降低生產成本並預先排除不良的晶圓,試圖在製程的前端提升生產效率。業界基於工程師的經驗有各種方法進行猜值,本研究期望建立一科學化的手法進行分析。
有別於一維數據資料分析,我們採取的方法為將晶圓的疊對誤差二維圖像化,進行誤差位移圖的相似度比對,嘗試以不一樣的角度分析資料。對於誤差位移圖的相似度比對問題,其最大的挑戰在於誤差位移方向及大小各異,不易使用傳統圖形辨識的方法。因此我們除了將晶圓做分群,更進一步探討不同生產路徑的晶圓層與層間的關係。欲預測晶圓的疊對誤差補償參數,可由前幾層的位移圖特徵,從歷史資料中找出最相似的路徑及晶圓當作參考。本研究以合作廠商所提供的資料進行實驗,期望能建立有效的科學預測方式,提升半導體晶圓的製程良率以及生產效率。
Overlay errors in lithography is derived from the offset of exposure, where errors are needed to be controlled within thresholds to maintain the yield of wafers. Through the measurements on wafers, scanners provide compensations for the purpose of correction and leave a fewer influence on back layers. However, it is time consuming and feckless for compensation due to repeated adjustment by measurement. Therefore, our goal focuses on the proper compensation prediction on correcting overlay errors, which also aims to eliminate defective wafers and analyze influenced factors in the front-end stage to improve the production efficiency. There have been a variety of methods for parameters prediction based on engineers’ experiences. In this study, we attempt to establish a scientific data-driven way for prediction analysis.
Here we aim to visualize numerical data from a different perspective; that is, transforming overlay errors into a map, comparing patterns caused by production errors using their similarity, and classifying similar patterns into clusters. The largest challenge of this problem is the diverse differences of overlay errors between wafers, which cannot be overcome by conventional approaches in the field of pattern recognition. Furthermore, we also explore the relationship between layers and layers in different production paths. Considering the parameter settings of unmeasured wafers, the visualization map from previous layers and other production conditions can be used to find the most similar wafers from historical data as a reference. It is inferred that the visualization map can provide proper parameter suggestions. This study is joint work with an industrial partner, and the goal aims at establishing effective approaches for improving yield in process and production efficiency.
第1章 、緒論 1
1.1 研究背景 1
1.2 研究動機與目的 2
1.3 研究架構與流程 3
第2章 、文獻回顧 5
2.1 微影製程 5
2.1.1 微影製程簡介 5
2.1.2 對準與曝光過程 5
2.1.3 曝光機台介紹 7
2.2 疊對誤差 8
2.2.1 疊對誤差定義 8
2.2.2 疊對誤差數學模型 9
2.2.3 補償參數 12
2.2.4 成效檢測方法 12
第3章 、圖像化分析手法 14
3.1 參數預測 14
3.2 資料二維圖像化 15
3.3 問題定義 16
3.4 相似度比對 17
3.4.1 定義比對單位 17
3.4.2 特徵定義 17
3.4.3 相似度計算 18
3.5 圖像化預測 20
3.5.1 參考路徑 20
3.5.2 權重與相似度分數 21
第4章 、實驗結果與分析 22
4.1 實驗數據 22
4.2 實驗分析手法 24
4.2.1 圖像結果分析 24
4.2.2 成效檢測方法 24
4.3 實驗結果 26
4.3.1 相似度比對圖 26
4.3.2 誤差位移圖 28
4.3.3 分數與排名 29
4.3.4 成效檢測 30
第5章 、結論與未來展望 34
5.1 結論 34
5.2 未來展望 35
參考文獻 36
[1]L.-C. Chao and L.-I. Tong, "Wafer defect pattern recognition by multi-class support vector machines by using a novel defect cluster index," Expert Systems with Applications, vol. 36, no. 6, pp. 10158-10167, 2009.
[2]S.-C. Hsu and C.-F. Chien, "Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing," International Journal of Production Economics, vol. 107, no. 1, pp. 88-103, 2007.
[3]蕭宏, 半導體製程技術導論(第三版). 全華圖書股份有限公司, 2014.
[4]M. Quirk and J. Serda, 半導體製造技術. 滄海圖書資訊股份有限公司, 2003.
[5]C.-F. Chien, K.-H. Chang, and C.-P. Chen, "Modeling overlay errors and sampling strategies to improve yield," Journal of the Chinese Institute of Industrial Engineers, vol. 18, no. 3, pp. 95-103, 2001.
[6]Z.-C. Lin and W.-J. Wu, "Multiple linear regression analysis of the overlay accuracy model," IEEE transactions on Semiconductor Manufacturing, vol. 12, no. 2, pp. 229-237, 1999.
[7]T. A. Brunner et al., "Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress," Journal of Micro/Nanolithography, MEMS, MOEMS, vol. 12, no. 4, p. 043002, 2013.
[8]Fabricating high-precision, multifunctional semiconductors. Available: https://www.nikon.com/products/semi/technology/story02.htm
[9]Y. Jiao and D. Djurdjanovic, "Stochastic control of multilayer overlay in lithography processes," IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 3, pp. 404-417, 2011.
[10]S.-C. Horng, "Compensating modeling overlay errors using the weighted least-squares estimation," IEEE Transactions on Semiconductor Manufacturing, vol. 27, no. 1, pp. 60-70, 2013.
[11]M. Van Den Brink, C. De Mol, and R. George, "Matching performance for multiple wafer steppers using an advanced metrology procedure," in Integrated Circuit Metrology, Inspection, and Process Control II, 1988, vol. 921, pp. 180-197: International Society for Optics and Photonics.
[12]D. S. Perloff, "A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers," IEEE Journal of Solid-State Circuits, vol. 13, no. 4, pp. 436-444, 1978.
[13]D. Ren et al., "Alignment Method for Linear-Scale Projection Lithography Based on CCD Image Analysis," Sensors, vol. 18, no. 8, p. 2442, 2018.
[14]P. N. Koch, R.-J. Yang, and L. Gu, "Design for six sigma through robust optimization," Structural and Multidisciplinary Optimization, vol. 26, no. 3-4, pp. 235-248, 2004.
[15]D. A. C. G. Keim, "Information visualization and visual data mining," IEEE transactions on Visualization, vol. 8, no. 1, pp. 1-8, 2002.
[16]D. H. Laidlaw et al., "Comparing 2D vector field visualization methods: A user study," IEEE Transactions on Visualization, vol. 11, no. 1, pp. 59-70, 2005.
[17]F. Hasibi, L. van Dijk, M. Larrañaga, A. Pastol, A. Lam, and R. van Haren, "Towards fab cycle time reduction by machine learning-based overlay metrology," in 34th European Mask and Lithography Conference, 2018, vol. 10775, p. 107750X: International Society for Optics and Photonics.

(此全文未開放授權)
電子全文
中英文摘要
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *