|
[1]L.-C. Chao and L.-I. Tong, "Wafer defect pattern recognition by multi-class support vector machines by using a novel defect cluster index," Expert Systems with Applications, vol. 36, no. 6, pp. 10158-10167, 2009. [2]S.-C. Hsu and C.-F. Chien, "Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing," International Journal of Production Economics, vol. 107, no. 1, pp. 88-103, 2007. [3]蕭宏, 半導體製程技術導論(第三版). 全華圖書股份有限公司, 2014. [4]M. Quirk and J. Serda, 半導體製造技術. 滄海圖書資訊股份有限公司, 2003. [5]C.-F. Chien, K.-H. Chang, and C.-P. Chen, "Modeling overlay errors and sampling strategies to improve yield," Journal of the Chinese Institute of Industrial Engineers, vol. 18, no. 3, pp. 95-103, 2001. [6]Z.-C. Lin and W.-J. Wu, "Multiple linear regression analysis of the overlay accuracy model," IEEE transactions on Semiconductor Manufacturing, vol. 12, no. 2, pp. 229-237, 1999. [7]T. A. Brunner et al., "Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress," Journal of Micro/Nanolithography, MEMS, MOEMS, vol. 12, no. 4, p. 043002, 2013. [8]Fabricating high-precision, multifunctional semiconductors. Available: https://www.nikon.com/products/semi/technology/story02.htm [9]Y. Jiao and D. Djurdjanovic, "Stochastic control of multilayer overlay in lithography processes," IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 3, pp. 404-417, 2011. [10]S.-C. Horng, "Compensating modeling overlay errors using the weighted least-squares estimation," IEEE Transactions on Semiconductor Manufacturing, vol. 27, no. 1, pp. 60-70, 2013. [11]M. Van Den Brink, C. De Mol, and R. George, "Matching performance for multiple wafer steppers using an advanced metrology procedure," in Integrated Circuit Metrology, Inspection, and Process Control II, 1988, vol. 921, pp. 180-197: International Society for Optics and Photonics. [12]D. S. Perloff, "A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers," IEEE Journal of Solid-State Circuits, vol. 13, no. 4, pp. 436-444, 1978. [13]D. Ren et al., "Alignment Method for Linear-Scale Projection Lithography Based on CCD Image Analysis," Sensors, vol. 18, no. 8, p. 2442, 2018. [14]P. N. Koch, R.-J. Yang, and L. Gu, "Design for six sigma through robust optimization," Structural and Multidisciplinary Optimization, vol. 26, no. 3-4, pp. 235-248, 2004. [15]D. A. C. G. Keim, "Information visualization and visual data mining," IEEE transactions on Visualization, vol. 8, no. 1, pp. 1-8, 2002. [16]D. H. Laidlaw et al., "Comparing 2D vector field visualization methods: A user study," IEEE Transactions on Visualization, vol. 11, no. 1, pp. 59-70, 2005. [17]F. Hasibi, L. van Dijk, M. Larrañaga, A. Pastol, A. Lam, and R. van Haren, "Towards fab cycle time reduction by machine learning-based overlay metrology," in 34th European Mask and Lithography Conference, 2018, vol. 10775, p. 107750X: International Society for Optics and Photonics.
|