隨著消費者對手持裝置與電子產品在輕薄化、高效能與多功能的需求下，以及半導體製程能力的不斷提高，使得晶片功能日益強大。然而隨著系統單晶片（System-on-Chip, SoC）生產成本越來越高，造成發展面臨瓶頸；反觀從整合度而言，系統級構裝（System-in-Package, SiP）技術隨著整合度的提高，應用範圍也越來越廣大以及挾帶眾多優勢。加上從系統端出發「小晶片」（Chiplet）設計概念的興起，藉由異質整合（Heterogeneous Integration, HI）技術，建立一個小晶片網路，達到結合傳統封裝技術的生產速度與靈活性，以及半導體技術的細間距與高效能等優點，成為異質整合系統構裝技術之目標。
異質整合涵蓋大量元件與複雜的架構，其製作成本、良率與發開時間均極度可觀。在本研究架構中，參考Intel的Lakefield產品架構，提出一具更高整合度之異質整合小晶片系統級構裝架構，為了在產品研發之前，能夠有效的針對結構進行分析、改良與尋找最佳的設計方式，減少試誤法（Try & Error）所造成的資源浪費，採用模擬設計技術（Design-on-Simulation Technology），搭配適當的熱傳與力學理論，以及經驗式來進行分析與設計。
首先，分析該結構的熱循環測試（Thermal Cycling Test, TCT）可靠性弱點。藉由幾何配置與材料搭配，推測錫球是架構中最有可能發生故障的位置。因此本研究首先使用晶圓級晶片尺寸封裝（Wafer Level Chip Scale Package, WLCSP）載具驗證模型的合理性和準確性。並藉由控制焊球的關鍵區域網格尺寸並使用 Coffin-Manson 經驗公式可以成功預測焊球的可靠性壽命。此外，探討剪切鎖定（shear lock）效應導致壽命被低估的問題。根據結果，採用簡化積分方法的 Solid-185 似乎解決了剪切鎖定問題，且因高斯積分點較少，因此模型壽命預估更具有效率。接著，藉由架構逐步演變，探索各構件的幾何對架構壽命的影響，為未來的架構設計改善提供參考。
對於容易造成多尺度問題的中介層與微凸塊層結構，進行等效架構驗證。此外，運算小晶片下方的熱介面材料層為本架構必要設計，可避免錫球接點非預期位置之過早失效。最後，考慮到多數異質整合架構均為非對稱性，若採用整個三維模型進行驗證，計算時間將顯著增加。並且結構設計優化時需要不斷重複模擬驗證，架構元素數量將嚴重影響運算效能。因此，採用全域-局部建模技術，在應力變化較為緩和的區域進行多點約束面設定，可有效減少全模型的元素數量，並且，在本研究中使用了雙層的多點約束面設定，使模型元素數量與運算時間減少至原本的35%與13%，大幅提升設計效率。
本研究旨在建立一個基於理論觀點的驗證程序來評估異構集成架構的散熱與可靠性。透過模擬驗證過程採用循序漸進的方法，對研究結構之散熱特性，以及因熱應力應變引起的疲勞失效進行驗證，包括架構的幾何和配置。並應用於快速估計和改進異質整合小芯片系統級封裝架構的散熱與可靠性性能。

Electronic devices require more efficiency and functionality, so the cost of producing a System on Chip (SoC) is prohibitive. System-in-Package (SiP) technology offers integration capabilities and combining it with Heterogeneous Integration (HI) technology creates small chip networks for fast production speeds and high precision in integrated systems. The "Chiplet" design concept utilizes HI technology for flexible and fast production while maintaining high performance through traditional packaging methods.
Heterogeneous integration covers many components and complex architecture, and its manufacturing cost, yield rate, and development time are incredibly considerable. Based on Intel's Lakefield product architecture, this study proposes a highly integrated chiplets system-level architecture for practical analysis and optimization before product development. By adopting the Design-on-Simulation Methodology, heat transfer and mechanical theories, and empirical methods, the design method reduces the waste of resources caused by trial and error.
Thermal management can verify the relevant thermal radiation and convection coefficients by comparing them with the literature. Moreover, a good heat dissipation analysis is obtained through equivalent model verification and heat dissipation path analysis.
On the other hand, the study analyzes the thermal cycling reliability weakness of the structure, with the solder ball identified as the most likely failure location. Therefore, WLCSP is used to verify the model's accuracy, and the Coffin-Manson empirical formula predicts the reliability life of the solder ball. Next, the shear locking problem is solved using Solid-185, and gradual evolution is used to explore the geometry's influence on the structure's life.
An equivalent architecture check is needed to verify an interposer and micro-bump layer prone to multi-scale problems. In addition, the thermal interface material layer under the computing chiplet is necessary to avoid premature failure of solder ball joints in unintended positions. Moreover, considering the asymmetric architectures, the entire 3D model for validation would significantly increase computation time. Additionally, repeated simulation verification is required for structural optimization, and the number of elements can significantly impact computing performance. Therefore, a double-layer multi-point constraint (MPC) method can reduce the model’s elements effectively. As a result, they are reducing the number of model elements and calculation time to 35% and 13% of the original, significantly improving design efficiency.
This study aims to establish a verification program based on theoretical viewpoints to evaluate the thermal and reliability of heterogeneous integrated architectures. Through the simulation verification process, a step-by-step approach is adopted to verify the heat dissipation characteristics of the research structure, as well as the fatigue failure caused by thermal stress and strain, including the geometry and configuration of the structure. It is also applied to quickly estimate and improve the heat dissipation and reliability performance of heterogeneous integrated chiplet system-in-package architectures.

Abstract ivi
摘要 iv
TABLE OF CONTENTS vi
LIST OF TABLES ix
LIST OF FIGURES xi
CHAPTER 1 1
INTRODUCTION 1
1.1 Motivation of Research 1
1.2 Literature Survey 1
1.2.1 Development status of Heterogeneous Chiplets Packaging 5
1.2.2 Thermal Analysis Based on FE model 13
1.2.3 Interconnections Reliability Prediction 14
1.2.4 Global-Local FEM 14
1.3 Goal and Methodology of Research 20
CHAPTER 2 23
FUNDAMENTAL THEORIES 23
2.1 Solder Joint Reflow Profile Prediction Theory 23
2.2 Fundamental Theory of Heat Transfer 25
2.2.1 Heat Transfer Phenomenon 26
2.2.2 Thermal Analysis of Electronic Packaging 29
2.3 Numerical Methods and Convergence Criteria 32
2.4 Creep mechanism 34
2.4.1 Garofalo-Arrhenius Creep Theory 39
2.4.2 Anand’s Model 43
2.5 Hardening Rule 42
2.5.1 Isotropic Hardening Rule 43
2.5.2 Kinematic Hardening Rule 43
2.5.3 Chaboche Model 44
2.6 Reliability Analysis of Packaging 46
2.6.1 Coffin-Manson Strain Method 47
2.6.2 Modified Energy Density Method 48
2.7 MPC (Multipoint Constraint) Discussion 49
2.7.1 Connecting Different Types of Units 50
2.7.2 Connecting Different Coarse Mesh 52
2.8 Equivalent Architecture Verification Theory 53
2.8.1 Equivalent Mechanical Properties 53
2.8.2 Equivalent Thermal conductivity 55
CHAPTER 3 57
DESIGN OF NOVEL CHIPLET PACKAGING STRUCTURE 57
3.1 Computing System Architecture Operation Mechanism 58
3.2 Introduction to Intel’s Lakefield Architecture 61
3.3 Development of a Heterogeneous Chiplet Packaging Structure 65
CHAPTER 4 75
THERMAL ANALYSIS FOR HETEROGENEOUS CHIPLET PACKAGING 75
4.1 Thermal Transfer Procedure Verification 77
4.2 Effective Model Verification 81
4.3 Heterogeneous Chiplets Packaging Verification 85
CHAPTER 5 97
RELIABILITY ASSESSMENT FOR HETEROGENEOUS CHIPLET PCKAGING 97
5.1 Finite Element Modeling for Mechanical Analysis and Experimental Verification on WLCSP 98
5.1.1 WLCSP Thermal Cycling Test 99
5.1.2 WLCSP Finite Element Model Establish 102
5.1.3 Verification of 2D Model Simulation and Experimental Results 108
5.1.4 Effect of shear lock 108
5.2 Mechanical analysis for heterogeneous chiplets packaging architecture 121
5.2.1 Effective verification 124
5.2.2 Multipoint constraint FEM validation 129
5.2.3 Study of heterogeneous chiplets packaging model and results discussion 133
CHAPTER 6 146
CONCLUSION AND RECOMMENDATIONS 146
6.1 Conclusions 146
6.2 Recommendations for future works 147

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