近年來，隨著製程技術不斷的進步，元件特徵尺寸微縮，透過不同結構或通道材料來改善電特性，可以克服短通道效應所造成的問題。
本論文研究分為兩部分為主軸，分別為更換通道材料與改變閘極結構，改善金氧半電晶體之電特性與可靠度。
第一部分，取代傳統鰭式電晶體中的矽材料，以矽與矽鍺交互堆疊的矽鍺超晶格為通道材料，提升載子遷移率，再以不同的低溫電漿處理介面，改善鍺材料漏電問題。從實驗結果來看，不論是p或n型鰭式電晶體，在經低溫NH3電漿後，對於導通電流、關閉電流、次臨界擺幅、可靠度測試，都有較好的表現。推測經低溫NH3電漿處理後，能有效抑制鍺的擴散和鈍化介面，使通道載子侷限在矽與矽鍺量子井內，以提升載子遷移率及元件電特性。
第二部分，以改變結構做平面式、鰭式以及全環繞式電晶體，比較其電特性。全環繞式電晶體能有較佳的導通電流、關閉電流、次臨界擺幅以及可靠度測試。推測全環繞式電晶體有著更好的靜電閘極控制能力。
最後，對平面式、鰭式以及全環繞式電晶體，經不同輻射傷害後，對電特性與可靠度進一步分析。以電容器而言，隨著輻射傷害的提升，使電容劣化，造成EOT上升與漏電流增加。以金氧半電晶體電特性而言，可以發現全環繞式電晶體對於輻射傷害的抵抗能力，優於平面式電晶體與鰭式電晶體，除此之外，發現輻射傷害對於元件都有一定的傷害，其中以源、汲極接面劣化最為嚴重。

In recent years, the short channel effect (SCE) with the shrinking feature size of MOSFETs was reduced and electrical characteristics can be improved by replacing material channel or gate structure.
This thesis can be divided into two parts. One is different channel materials; the other is different gate structures of FinFET. Two approaches are studied to improve electrical characteristics and reliability.
In the first part, since Ge can provide higher carrier mobility than Si, the high performance of FinFET can be achieved by using Si/SiGe super-lattice channel. However, leakage current of Ge-based device is higher due to more Ge diffusion. Therefore, low temperature (NH3/H2) plasma treatments were applied on channel surface to suppress gate leakage. After NH3 plasma treatment, both the n-FinFET and p-FinFET exhibit higher on drive current, lower off current, smaller sub-threshold swing, and better reliability. It indicates that Si/SiGe super-lattice channel can be passivated by NH3 plasma treatment. Hence, the carrier can be effectively confined in the quantum well between Si and SiGe.
In the second part, the effects of different MOSFET structures are studied. The results suggest that GAAFET shows better electrical characteristics than FinFET and planar MOSFET. This indicates that the structure of GAAFET has superior control ability of the electrostatic in gate stack.
Finally, the effects of radiation damage on different MOSFET structures are studied. With increasing radiation damage, the degradation of gate capacitance in MOS device is observed. It leads to higher EOT and higher leakage current. As a result, GAAFET shows better radiation hardness. Moreover,it is found that the radiation damage to source/drain junction is more, as compared to that on gate dielectrics.

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 xiii
第一章 序論 1
1.1 前言 1
1.2 高介電材料(High-k)介紹 1
1.3 高介電材料的選擇 2
1.4 矽鍺虛擬基板-應變通道 3
1.4.1 臨界厚度 4
1.4.2 差排 4
1.5 絕緣層覆矽基板 5
1.6 鰭式電晶體(FinFET)、全環繞式電晶體(GAAFET) 5
1.7 輻射傷害 6
1.8 論文架構 6
第二章 元件製程與量測 21
2.1 SOI 電晶體製作流程 21
2.1.1 晶圓刻號與清潔 21
2.1.2 晶圓對準記號形成 21
2.1.3 主動區形成 22
2.1.4 閘極介電層沉積 22
2.1.5 金屬閘電極的形成 22
2.1.6 源極(Source)、汲極(Drain)、基極(Base)的形成 22
2.1.7 鈍化層沉積 23
2.1.8 金屬導線、燒結 23
2.2 電性的量測 23
2.2.1 電晶體電流-電壓(I-V)特性量測 23
2.2.2 電容-電壓(C-V)量測與模擬 24
2.3 物性分析 24
2.3.1 穿透式電子顯微鏡 24
第三章 應用於不同低溫氣體電漿對矽鍺超晶格通道處理之鰭式電晶體之電性分析 …………………………………………………………………………..31
3.1 研究動機 31
3.2 製程與量測 32
3.2.1 製程流程條件 32
3.2.2 量測參數 33
3.3 實驗結果與討論 33
3.3.1 不同低溫氣體電漿處理對矽鍺超晶格通道之電容器之電特性分析 …………………………………………………………………..34
3.3.2 不同低溫氣體電漿對矽鍺超晶格通道處理之鰭式電晶體之電特性分析 34
3.4 本章結論 36
第四章 平面、鰭式、全環繞式電晶體之電特性研究 49
4.1 研究動機 49
4.2 製程與量測 51
4.2.1 製程條件 51
4.2.2 量測參數 51
4.3 實驗結果與討論 52
4.3.1 平面、鰭式、全環繞式電晶體在穿透式電子顯微鏡下的分析 …………………………………………………………………..52
4.3.2 金氧半電晶體之電容器之電特性分析 53
4.3.3 平面、鰭式、全環繞式電晶體之電特性分析 53
4.4 本章結論 56
第五章 平面、鰭式、全環繞式電晶體經輻射傷害之可靠度研究 74
5.1 研究動機 75
5.2 製程與量測 75
5.2.1 製程條件 75
5.2.2 量測參數 76
5.3 實驗結果與討論 76
5.3.1 不同輻射傷害對電容器之電特性分析 77
5.3.2 平面、鰭式、全環繞式電晶體經輻射傷害之電特性分析 78
5.4 本章結論 84
第六章 結論與未來展望 120
6.1 結論 120
6.2 未來展望 121
參考文獻 122

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