隨著技術的進步，近年來的大多數數據計算和傳輸都可以在數位領域完成，並且許多複雜的運算可以經由數位信號處理輕鬆實現。因此，類比數位轉換器（一種可以將類比訊號轉換成數位訊號的媒介）變得越來越重要。
由於連續漸進式類比數位轉換器的低功率消耗特性及容易使用各種先進製程實現，連續漸進式類比數位轉換器在眾多類比數位轉換器架構中，越來越獲得青睞。由於連續漸進式類比數位轉換器的低功耗特性以及易於使用各種先進製程實現。本論文提出了一個簡化的控制電路以節省類比數位轉換器的功率消耗。
在本論文中，吾人提出了一種簡化的SAR控制電路，以減少連續漸進式類比數位轉換器的功耗。為了驗證所提出的SAR控制電路，使用90 nm CMOS製程設計了一個10位連續漸進式類比數位轉換器。模擬結果顯示，信噪諧波比為61.21 dB，相當於9.87 ENOB。模擬的最大DNL為0.223 / -0.185 LSB，最大INL為0.312 / -0.369LSB。 平均功耗為84.5 W。 晶片面積為805 μm × 699 μm，核心電路晶片面積為356 μm × 203 μm。

With the advancement of technology, most of the data calculation and transmission in recent years can be completed in the digital field, and many complex operations can be easily achieved via digital signal processing. Therefore, in most of today's digital circuits, the analog-to-digital converter, a medium that can convert analog signals into digital signals, becomes more important. Due to the low power consumption characteristics of Successive-Approximation-Register analog-to-digital converter (SAR ADC) and the ease of implementation using various advanced processes, SAR ADCs are becoming increasingly popular in many analog-to-digital converter architectures.
In this work, a simplified SAR control circuit is proposed to reduce the power consumption of SAR ADCs. To verify the proposed control circuit, a 10-bit SAR ADC was designed using 90 nm CMOS technology. The simulation results show that the signal to noise and harmonic ratio is 61.21 dB, which is equivalent to 9.87 ENOB. The simulated maximal DNL is 0.223/-0.185 LSB, and the maximal INL is 0.312/-0.369LSB. The average power consumption is 84.5 W. The chip area is 805 m × 699 m and the core circuit area is 356 m × 203 m.

中文摘要 i
Abstract ii
目錄 iii
圖目錄 vii
表目錄 xi
第一章 緒論 1
1.1 研究動機(Motivation) 1
1.2 論文結構 2
第二章 類比數位轉換器參數與原理 3
2.1 類比數位轉換器參數介紹 3
2.1.1 取樣率(Sampling Rate) 3
2.1.2 解析度(Resolution) 4
2.1.3 最低有效位元(Least Signification Bit) 4
2.1.4 量化誤差(Quantization Error) 4
2.1.5 差分非線性度(Differential Nonlinearity) 6
2.1.6 積分非線性度(Integral Nonlinearity) 7
2.1.7 直流偏差 (DC offset) 8
2.1.8 增益誤差 (Gain Error) 8
2.1.9 遺失碼 (Missing Codes) 9
2.1.10 訊號雜訊比 (Signal-to-Noise Ratio) 10
2.1.11 總諧波失真(Total Harmonic Distortion) 11
2.1.12 無雜訊動態範圍(Spurios Free Dynamic Range) 11
2.1.13 訊號與雜訊諧波比(Signal-to-Noise and Distortion Ratio) 12
2.1.14 動態範圍(Dynamic Range) 12
2.1.15 有效位元數(Effective Number of Bits) 13
2.1.16有效解析頻寬(Effective Resolution Bandwidth) 13
2.1.16 價值指標(Figure of Merit) 14
2.2 類比數位轉換器架構 14
2.2.1 快閃式類比數位轉換器(Flash ADC) 15
2.2.2 管線式類比數位轉換器(Pipelined ADC) 16
2.2.3 連續漸進式類比數位轉換器(Successive Approximation Register ADC) 18
2.2.4 三角積分類比數位轉換器(Delta-Sigma ADC) 20
2.3 類比數位轉換器選擇 21
第三章 連續漸進式類比數位轉換器概論 24
3.1 連續漸進式類比數位轉換器簡介 24
3.2 取樣及保持電路(Sample and Hold) 24
3.2.1 熱雜訊(Thermal Noise) 25
3.2.2 電荷注入效應(Charge injection) 25
3.2.3 時脈饋入效應(Clock feedthough) 26
3.2.4 電晶體開關(Switch) 27
3.3 比較器(Comparator) 30
3.3.1 操作速度(Speed) 30
3.3.2 輸入電壓偏移(Input Offset) 30
3.3.3 精準度(Accuracy) 31
3.3.4 回踢雜訊(Kickback Noise) 31
3.4 數位類比轉換器 32
3.4.1 傳統式電容切換演算法(Conventional switching algorithm) 34
3.4.2 單調性電容切換演算法(Monotonic switching algorithm) 35
3.4.3 電容拆半切換演算法(Split-Capacitor switching algorithm) 36
3.4.4 共模切換演算法(Merged-Capacitor switching algorithm) 37
3.5 連續漸進式暫存器 39
3.6 帶冗餘位演算法 40
3.6.1 基本概念 40
3.6.2 非二進制搜索(Sub-Radix-2 Search) 41
3.6.3 外加式數位修正(ADEC) 42
3.6.4 容錯範圍(Error Tolerance Range) 43
第四章 帶冗餘位連續漸進式電路設計與實現 45
4.1 共模切換演算法之連續漸進式類比數位轉換器 45
4.1.1 靴帶式開關(Bootstrapped Switch) 47
4.1.2 比較器 (Comparator) 52
4.1.3 控制時脈產生器 55
4.1.4 開關控制邏輯 61
4.1.5 電容矩陣(Capacitor Array) 64
4.2 連續漸進式類比數位轉換器之模擬驗證 68
4.2.1 佈局前模擬 68
4.2.2 晶片佈局 71
4.2.3 佈局後模擬 72
4.2.4 晶片量測環境 74
第五章 結論與未來展望 75
5.1 結論 75
5.2 未來展望 75
A. 附錄 76
參考文獻 80

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