近年來，電子產品的生活化帶動了電子產業的發展進而使得半導體變成我們日常生活中不可或缺的部分。現在的電子產品的需求越來越多元，不僅需要高速、高效能還要體積小、低耗能且低成本，所以在目前的半導體技術上微縮、高密度被視為是一個技術世代的演進。然而在微縮尺度逼近一個臨界值的現在，有許多的挑戰等著要去克服，許多研究者提出符合未來發展趨勢的新應用，在新的世代之中使用高遷移率的材料來取代傳統的矽來做為通道的材料目的在於提高電晶體的效能，另一方面，降低功耗也是未來元件的一個重要指標。
在本篇論文中提到了在絕緣的矽基板上面製作鍺通道的多閘極式的電晶體，結合鐵電材料的閘極氧化層來製作高功率的元件，與現在的產業發展結合能運用在小奈米尺度之下的電晶體製造技術，不僅延續了摩爾定律還具備了產業應用的價值，本篇論文包含了元件的製造流程、基礎的電性分析以及物性的分析。主要的元件是以鍺通道為主體在搭配鐵電的負電容效應進行物性和電性的討論，首先電容成功證實了鐵電極化的現象接下來將探討P型奈米薄片的電晶體， 最後N型的元件也成功的實現。這個鐵電負電容的電晶體由於本身的電壓放大的特性使得臨界電壓下降來改善次臨界擺幅(subthreshold swing)被視為是進入下個世代突破次臨界擺幅物理極限的重要候選人。
這個研究中所提出來的鍺環繞式閘極奈米線通道之鐵電電晶體，有良好的電晶體特性，再加上製程簡單這個優點，相信對於未來的應用有很大的幫助。

In recent years, the using of electronic products has driven the development of the electronics industry and made semiconductors an indispensable part of our daily lives. The demand for electronic products is becoming more and more diverse, requiring not only high speed, high efficiency, but also small size, low power consumption, and low cost. Therefore, the scaling down of the dimension and high density on the single wafer are regarded as an evolution of a technological generation. However, now that the scale is approaching a critical value, many challenges are waiting to be overcome. Many researchers propose new applications that are in line with future trends, using high mobility materials to replace traditional ones in the new generation. The material used as a channel is to improve the performance of the transistor. On the other hand, reducing power consumption is also an important indicator of the device in the future.
In this paper, a gate-all-around transistor with a germanium channel formed on Silicon on Insulator (SOI) wafer is combined with a gate oxide layer of ferroelectric material to fabricate high-performance components, which can be used in combination with the industrial development. The transistor manufacturing technology under the small nanoscale not only extend the life of Moore's Law but also has the value of the industrial application. This paper contains the manufacturing process of components, the basic electrical analysis and the analysis of physical properties. The main point is the discussion of the physical properties and electrical properties of the germanium channel with the negative capacitance effect of ferroelectric. First, the capacitance also successfully proofs the phenomenon of polarization within the ferroelectricity layer, and then the transistor of the P-type nanosheet will be discussed. Finally, the N-type device will be successfully realized. This ferroelectric negative-capacitance transistor, due to its voltage-amplifying characteristics, causes the threshold voltage to shift to improve the subthreshold swing, and this result makes it become an important candidate for the next generation to break through the physical limits of the subthreshold swing.
The Germanium Gate-all-around Nanowire Ferroelectricity Field-Effect-Transistor proposed in this study has good transistor characteristics, and the advantage of a simple process is believed to be of great help for future applications.

中文摘要..........................................................i
Abstract.......................................................iii
Acknowledge......................................................v
Contents........................................................vi
Table Captions.................................................vii
Figure Captions...............................................viii
Chapter 1....................................................- 1 -
Introduction.................................................- 1 -
1-1 Challenge of Moore’s law.................................- 1 -
1-2 High mobility channel materials..........................- 4 -
1-3 Germanium based field effect transistor..................- 6 -
1-4 High-κ as gate oxide for Germanium device................- 9 -
1-5 Negative capacitance effect on ferroelectricity device..- 13 -
1-6 Motivation..............................................- 16 -
1-7 Thesis Organization.....................................- 21 -
Chapter 2...................................................- 22 -
Mechanism of the MOSFET.....................................- 22 -
2-1 Basic Principle of MOSFET...............................- 22 -
2-2 MOS Parameters Extraction...............................- 24 -
A. Threshold voltage (Vth)..................................- 24 -
B. Subthreshold swing (SS)..................................- 24 -
C. ON/OFF current ratio(Ion/Ioff)...........................- 25 -
D. Drain Induced Barrier Lowering(DIBL).....................- 25 -
Chapter 3...................................................- 27 -
Capacitance with ferroelectricity layer.....................- 27 -
3-1 Fabrication Process.....................................- 27 -
3-2 Images Analysis.........................................- 30 -
3-3 Characteristic Analysis.................................- 31 -
3-3-1 X-ray photoelectron spectroscopy (XPS)................- 31 -
3-3-2 Polarization and Hysteresis...........................- 33 -
Chapter 4...................................................- 36 -
Ge GAA Nanosheet P-type FE-FET..............................- 36 -
4-1 Device Fabrication Process..............................- 36 -
4-2 Images Analysis.........................................- 40 -
4-2-1 FIB image of the device structure.....................- 40 -
4-2-2 TEM image of the device structure.....................- 41 -
4-3 Characteristic Analysis.................................- 45 -
Chapter 5...................................................- 50 -
Ge GAA Nanosheet N-type FE-FET..............................- 50 -
5-1 Device Fabrication Process..............................- 50 -
5-2 Images Analysis.........................................- 54 -
5-2-1 FIB image of the device structure.....................- 54 -
5-2-2 TEM image of the device structure.....................- 55 -
5-3 Characteristic Analysis.................................- 60 -
5-4 Summary of the P-type and N-type Device in This Study...- 66 -

Conclusion..................................................- 67 -
Reference...................................................- 68 -

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