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Chapter 1 [1-1] IBM’s roadmap for 14nm, 10nm and 7nm [1-2] International Roadmap for Devices and Systems (IRDS™) 2017 Edition [1-3] MORE MOORE S. Takagi et al., "Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance," IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 21-39, 2008. [1-4] J. Feng, R. Woo, S. Chen, Y. Liu, P. B. Griffin, and J. D. Plummer, "P-Channel Germanium FinFET Based on Rapid Melt Growth," IEEE Electron Device Letters, vol. 28, no. 7, pp. 637-639, 2007. [1-5] B. Liu et al., "High-Performance Germanium$\Omega$-Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack," IEEE Electron Device Letters, vol. 33, no. 10, pp. 1336-1338, 2012. [1-6] C. Chung, C. Chen, J. Lin, C. Wu, C. Chien, and G. Luo, "First experimental Ge CMOS FinFETs directly on SOI substrate," in 2012 International Electron Devices Meeting, 2012, pp. 16.4.1-16.4.4. [1-7] Y. Nakakita, R. Nakakne, T. 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Wu, P. Su, C. Chang, and M. Hung, "Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure," IEEE Electron Device Letters, vol. 29, no. 11, pp. 1226-1228, 2008. [1-12] Y.-H. Wu, J.-R. Wu, M.-L. Wu, L. Chen, and C.-C. Lin, Ge-Based Nonvolatile Memory Formed on Si Substrate with Ge-Stabilized Tetragonal ZrO2 as Charge Trapping Layer. 2011, p. H410. [1-13] M. Yeh et al., "Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory," IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 814-819, 2014. [1-14] M.-S. Yeh et al., "A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory," Nanoscale Research Letters, vol. 9, no. 1, p. 603, 2014/11/06 2014. [1-15] M.-S. Yeh et al., "Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory," Nanoscale Research Letters, vol. 8, no. 1, p. 331, 2013/07/22 2013. Chapter 2 [2-1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells-an overview," Proceedings of the IEEE, vol. 85, no. 8, pp. 1248-1271, 1997. [2-2] Sze, Simon M., and Kwok K. Ng. Physics of semiconductor devices. John wiley & sons, 2006. [2-3] M. Lenzlinger and E. H. Snow, "Fowler‐Nordheim Tunneling into Thermally Grown SiO2," Journal of Applied Physics, vol. 40, no. 1, pp. 278-283, 1969/01/01 1969. [2-4] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, Failure mechanisms of flash cell in program/erase cycling. 1995, pp. 291-294. [2-5] 2008_Nonvolatile Memory Technologies with Emphasis on Flash edited by Mr. Joe E. Brewer Master of Science degree in Electrical Engineering, Dr. Manzur Gill Ph.D. in Electrical Engineering, [2-6] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, 2003. Chapter 3 [3-1] M. Yeh et al., "Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment," IEEE Journal of the Electron Devices Society, vol. 6, pp. 1227-1232, 2018. [3-2] Q. Xie et al., "Germanium surface passivation and atomic layer deposition of high-kdielectrics—a tutorial review on Ge-based MOS capacitors," Semiconductor Science and Technology, vol. 27, no. 7, p. 074012, 2012/06/22 2012. [3-3] M. Botzakaki et al., Interfacial Properties of ALD-Deposited Al2O3/p-Type Germanium MOS Structures: Influence of Oxidized Ge Interfacial Layer Dependent on Al2O3 Thickness. 2012, p. 32. [3-4] E. Shigesawa et al., "Study on Al2O3/Ge interface formed by ALD directly on epitaxial Ge," Semiconductor Science and Technology, vol. 33, no. 12, p. 124020, 2018/11/20 2018. [3-5] R. Degraeve et al., "Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks," in 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-4. [3-6] Y. Lee et al., "Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing," IEEE Electron Device Letters, vol. 32, no. 2, pp. 194-196, 2011. Chapter 4 [4-1] L. Milani, F. Torricelli, and Z. M. Kovács-Vajna, "Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications," IEEE Transactions on Electron Devices, vol. 62, no. 10, pp. 3237-3243, 2015. [4-2] Joe E. Brewer and Manzur Gill, Nonvolatile Memory Technologies with Emphasis on Flash, 1st ed., IEEE press, 2008, ch. 13, pp.623.
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