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[1] S. M. Sze et al., Physics of semiconductor devices. John Wiley & Sons, 2006. [2] M. L. French et al., "Design and scaling of a SONOS multi-dielectric device for nonvolatile memory applications," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, vol. 17, no. 3, pp. 390-397, 1994. [3] K. T. San et al., "Effects of erase source bias on Flash EPROM device reliability," IEEE Transactions on Electron Devices, vol. 42, no. 1, pp. 150-159, 1995 [4] M. H. White et al., "On the go with SONOS," IEEE Circuits and Devices Magazine, vol. 16, no. 4, pp. 22-31, 2000. [5] J. Bu et al., "Retention reliability enhanced SONOS NVSM with scaled programming voltage," Aerospace Conference Proceedings, Big Sky, MT, 2002. [6] M. H. White et al., "A low voltage SONOS nonvolatile semiconductor memory technology," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, vol. 20, no. 2, pp. 190-195, 1997. [7] D. Kahng et al., "A floating gate and its application to memory devices," Bell Labs Technical Journal, vol. 46, no. 6, pp. 1288-1295, 1967. [8] N. Yamauchi et al., "Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film," IEEE Transactions on Electron Devices, vol. 38, no. 1, pp. 55-60, 1991. [9] S. Jagar et al., "Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization," International Electron Devices Meeting, Washington, 1999. [10] M. K. Hatalis et al., "Large grain polycrystalline silicon by low‐temperature annealing of low‐pressure chemical vapor deposited amorphous silicon films," Journal of applied physics, vol. 63, no. 7, pp. 2260-2266, 1988. [11] D. K. Schroder, Semiconductor material and device characterization. John Wiley & Sons, 2006. [12] C.-H. Fu et al., "Enhanced hole mobility and low Tinv for pMOSFET by a novel epitaxial Si/Ge superlattice channel," IEEE Electron Device Letters, vol. 33, no. 2, pp. 188-190, 2012. [13] S. Maikap et al., "Characteristics of strained-germanium p-and n-channel field effect transistors on a Si (1 1 1) substrate," semiconductor science and technology, vol. 22, no. 4, pp. 342, 2007. [14] Y. Kamata et al., “Superior Cut-Off Characteristics of Lg=40nm Wfin=7nm Poly Ge Junctionless Tri-gate FET for Stacked 3D Circuits Integration” IEEE Transactions on Very Large Scale Integration systems, vol. 21, 2013 [15] C. W. Chen et al., “High-performance germanium p- and n-MOSFETs with NiGe source/drain,” IEEE Transactions on Electron Devices, vol. 61, pp. 2656-2661, 2014. [16] Q. C. Zhang et al, “Drive-current enhancement in Ge n-channel MOSFET using laser annealing for source/drain activation,” IEEE Electron Device Letters, vol. 27, pp. 728-730, 2006. [17] R. Duffy and M. Shayesteh, ”Germanium doping, contacts, and thin-body structures,” Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3- and-Tutorials in Nanotechnology: Dielectrics in Nano systems Applications 4, vol. 45, pp. 189-201,2012. [18] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices. Hoboken, NJ, USA: Wiley, 2007. [19] E. Simoen et al, , “Ion-implantation issues in the formation of shallow junctions in germanium,” Materials Science in Semiconductor Processing, vol. 9, pp. 634-639, 2006. [20] J. D. Huang et al, “Germanium n+/p junction formation by laser thermal process,” Applied Physics Letters, vol. 87, pp. 173507-1-173507-3, 2005. [21] T.-H. Hsu et al., "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," International Electron Devices Meeting, Washington,2007 [22] J. Fu et al., "Si-nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si) nonvolatile memory cell," European solid-state device research conference, Edinburgh, 2008. [23] Y.-N. Tan et al., "Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer," IEEE Transactions on Electron Devices, vol. 51, no. 7, pp. 1143-1147, 2004. [24] M. S. Joo et al., "Formation of hafnium-aluminum-oxide gate dielectric using single cocktail liquid source in MOCVD process," IEEE Transactions on Electron Devices, vol. 50, no. 10, pp. 2088-2094, 2003. [25] H.-T. Lue et al., "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," International Electron Devices Meeting, Washington,2005. [26] Z.-H. Ye et al., "A novel SONOS-type flash device with stacked charge trapping layer," Microelectronic Engineering, vol. 86, no. 7-9, pp. 1863-1865, 2009. [27] P.-H. Tsai et al., “Charge-trapping-type flash memory device with stacked high-k charge-trapping layer,” IEEE Electron Device Letters, vol. 30, no. 7, pp. 775–777, 2009. [28] P. H. Tsai et al., “Novel SONOS-type nonvolatile memory device with optimal Al doping in HfAlO charge-trapping layer,” IEEE Electron Device Letters, vol. 29, no. 3, pp. 265–268,2008. [29] J. P. Colinge et al., ”Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions,” Science of Advanced Materials, vol. 3, pp. 477-482, 2011. [30] J. P. Colinge et al., “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, pp. 225-229, 2010. [31] C. J. Su et al., “A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires,” Nanoscale Research Letters, vol. 7, pp. 1-6, 2012. [32] H. T. Lue et al, “A novel buried-channel FinFET BE-SONOS NAND flash with improved memory window and cycling endurance,” Symposium on VLSI Technology, 2009. [33] J. H. You et al., "Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices," Simulation of Semiconductor Processes and Devices, 2011 [34] D. Kahng et al., "A floating gate and its application to memory devices," " Bell Labs Technical Journal, vol. 46, no. 6, pp. 1288-1295, 1967. [35] H. P. Belgal et al., "A new reliability model for post-cycling charge retention of flash memories," IEEE International Reliability Physics Symposium. Proceedings. 2002, pp. 7-20. [36] A. Rothschild et al., "O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory," Solid State Device Research Conference, European, 2009, pp. 272-275. [37] A. Paul et al., "Comprehensive simulation of program, erase and retention in charge trapping flash memories," International Electron Devices Meeting, Washington, 2006. [38] J. H. You et al., "Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices," Simulation of Semiconductor Devices and Processes, 2011, pp. 199-202. [39] Y. Sun et al.,” Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity” IEEE Transactions on Electron Devices, vol.58, pp. 1329-1335, 2011. [40] Y. Kamata et al, , “Superior cut-off characteristics of Lg=40nm Wfin=7nm poly Ge junctionless tri-gate FET for stacked 3D circuits integration,” Symposium on VLSI Technology, 2013. [41] K. Usuda et al.,” High-Performance Tri-Gate Poly-Ge Junction-Less P- and N-MOSFETs Fabricated by Flash Lamp Annealing Process,” International Electron Devices Meeting, Washington, 2014. [42] Mengnan Ke et al., ” Impact of atomic layer deposition high k films on slow trap density in Ge Mos interfaces with GeOx interfacial layers formed by plasma pre-oxidation,” IEEE Journal of the Electron Devices Society, pp 950-955, 2018 [43] Shinichi Takagi et la., “Ge gate stacks based on Ge oxide interfacial layers and the impact on MOS device properties,” Journal Microelectronic Engineering, vol. 109, pp.389-39, 2013. [44] C.H. Shin et al., “Nitrogen effect on negative fixed charges of Al2O3 passivation film in crystalline Si solar cells,” Conference Record of the IEEE Photovoltaic Specialists Conference,2010 [45] Yujin Seo et al., “Investigation of Border Trap Characteristics in the AlON/GeO2/Ge Gate Stacks” IEEE Transactions on Electron Devices, pp3998-4001, 2017. [46] Yew Heng Tan et al., “Al2O3 interface engineering of germanium epitaxial layer grown directly on silicon,” IEEE Transactions on Electron Devices, pp.56-62, 2013 [47] Heiji Watanabe et al., ”High-quality GeON gate dielectrics formed by plasma nitridation of ultrathin thermal oxides on Ge(100),” Solid-State and Integrated Circuit Technology, 2010.
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