近年來，隨著功率元件的普及，順應積體化的需求，將功率元件與低壓元件整合於同一晶片上日益重要，因此LDMOS成為主要的高壓元件。LDMOS具有橫向的漂移區結構，為其提供高耐壓的關鍵所在，但是高耐壓常由低摻雜濃度所提供，將導致導通電阻的上升，因此提供高耐壓與低導通電阻的訴求將為LDMOS設計中最重要的一環。
傳統高功率元件常利用RESURF的原理設計LDMOS，從Single RESURF, Double RESURF到Triple RESURF LDMOS，對於元件的改良主要著重在於漂移區內的結構，RESURF原理主要是提供元件空乏改善的方式，而從Single RE-SURF至Triple RESUR的演變中，除了提供高耐壓之餘，藉由P埋藏層位置的移動，來提供額外的電流通道來達成降低導通電阻，但也相對地開始令製程逐漸複雜。
本篇論文為了改善Triple RESURF結構下的導通電阻，並維持在600V的高耐壓需求，將提出Multi RESURF LDMOS元件結構，經由電腦模擬(Synopsys TCAD Sentaurus)對於元件結構參數調變並討論其所帶來的影響，進而找出最佳的設計參數，最後將推導BV與Ron,sp的關係式，提供設計者有明確的方向與資訊來設計合適的RESURF LDMOS。

As the power devices developing, integrated technology between the power de-vices and the general logic devices was more important than before. To stratify the inte-grated requirement, the LDMOS were universalized in power electronics. The lateral dirt region in the LDMOS is the key point to provide the high breakdown voltage. To provide the breakdown voltage, we need the lower doping concentration in the drift re-gion. The lower doping concentration cause the higher on-state resistance. The tradeoff question is the most important point of the LDMOS design.
RESURF(Reduced Surface Field) principle was the common used in the LDMOS design. From the Single RESURF LDMOS to the Triple RESURF LDMOS, we fo-cused on the improvement of the drift region structure. RESURF principle provides the design method to improve the depletion situation in the device. As the p buried layer was moved from the surface of the silicon wafer to the middle position of the n well, we got the extra current path to reduce the on-state resistance and the complex process.
To get the lower on-state resistance and keep the high breakdown voltage 600V, we provide the novel Multi RESURF LDMOS to improve the drift region structure. By the TCAD simulation (Synopsys TCAD Sentaurus), we discuss the influence of multi RESURF structure and optimize the design parameter. After the optimization, we found the best structure with the better FOM= 7.0MW/cm2, Ron,sp =59.6mohm∙cm^2 and Breakdown voltage = 646V.

致謝 ii
摘要 iii
Abstract iv
目次 iv
圖次 vi
第一章 序論 8
1.1 研究動機 8
1.2 章節大綱 9
第二章 元件結構與模擬模型 10
2.1 LDMOS的結構 10
2.2 LDMOS耐壓機制與導通機制 11
2.3 LDMOS的發展 12
2.3.1 RESURF原理 12
2.3.2 邊緣效應與接面崩潰 13
2.4 耐壓元件之崩潰機制 15
2.4.1 Zener崩潰 15
2.4.2 累增崩潰 15
2.4.3 介電層崩潰 17
2.5 小結 17
第三章 模擬環境與元件電性模擬 21
3.1 模擬軟體環境與流程介紹 21
3.2 RESURF元件結構 23
3.3 Triple RESURF LDMOS元件特性模擬 24
3.3.1 Triple RESURF LDMOS基本電性 24
3.3.2 Triple RESURF LDMOS崩潰模擬特性分析 25
3.3.3 Triple RESURF LDMOS 導通模擬特性分析 27
3.4 小結 28
第四章 Multi RESURF LDMOS電性模擬 41
4.1 Multi RESURF LDMOS元件結構 41
4.2 Multi RESURF LDMOS元件崩潰模擬與電性分析 42
4.3 Multi RESURF LDMOS元件導通模擬與電性分析 43
4.4 分析與討論 44
第五章 結論 54
參考文獻 56

[1] Baliga, B. Jayant. "An overview of smart power technology." IEEE Transactions on Electron devices 38.7 (1991): 1568-1575.
[2] KOBAYASHI, T., et al. High-voltage power MOSFETs reached almost to the sil-icon limit. In: Power Semiconductor Devices and ICs, 2001. ISPSD'01. Proceed-ings of the 13th International Symposiμm on. IEEE, 2001. p. 435-438.
[3] APPELS, J. A.; VAES, H. M. J. High voltage thin layer devices (RESURF de-vices). In: Electron Devices Meeting, 1979 Internationa. IEEE, 1979. p. 238-241.
[4] PARPIA, A.; SALAMA, C. Andre T. Optimization of RESURF LDMOS tran-sistors: an analytical approach. IEEE transactions on electron devices, 1990, 37.3: 789-796.
[5] KAO, Y. C.; WOLLEY, E. D. High-voltage planar pn junctions. Proceedings of the IEEE, 1967, 55.8: 1409-1414.
[6] AKHTAR, J.; AHMAD, S. Breakdown voltage of a rectangular planar diffused junction with rounded corners. IEEE Transactions on Electron Devices, 1984, 31.12: 1781-1783.
[7] Baliga, B. Jayant. Fundamentals of power semiconductor devices. Springer Sci-ence & Business Media, 2010.
[8] STOJADINOVI, N. D.; RISTI, Lj Dj; VIDANOVI, B. V. New technique for fabrication of low voltage Si Zener diodes. Electronics Letters, 1981, 17.3: 130-132.
[9] WONG, Hei. A physically-based MOS transistor avalanche breakdown model. IEEE transactions on electron devices, 1995, 42.12: 2197-2202.
[10] SATAKE, H.; TORIΜMI, A. Dielectric breakdown mechanism of thin-SiO2 studied by the post-breakdown resistance statistics VLSI Tech. Dig. Tech. Papers, 1999, 61-61.
[11] LUDIKHUIZE, Adriaan W. A review of RESURF technology. In: Power Semi-conductor Devices and ICs, 2000. Proceedings. The 12th International Sympo-siμm on. IEEE, 2000. p. 11-18.
[12] HOSSAIN, Zia, et al. Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance. In: Power Semiconductor Devices and ICs, 2002. Pro-ceedings of the 14th International Symposiμm on. IEEE, 2002. p. 137-140.
[13] DISNEY, D. R. A new 600V lateral PMOS device with a buried conduction layer. In: Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD'03. 2003 IEEE 15th International Symposiμm on. IEEE, 2003. p. 41-44.
[14] QIAO, Ming, et al. A 700-V junction-isolated triple RESURF LDMOS with n-type top layer. IEEE Electron Device Letters, 2014, 35.7: 774-776.
[15] CHOI, E. K.; CHOI, Y. I.; CHUNG, S. K. Breakdown voltage and on-resistance of multi-RESURF LDMOS. Microelectronics journal, 2003, 34.5-8: 683-686.
[16] BALIGA, B. Jayant. Power semiconductor device figure of merit for high-frequency applications. IEEE Electron Device Letters, 1989, 10.10: 455-457.
[17] IQBAL, Md Mash-Hud; UDREA, Florin; NAPOLI, Ettore. On the static perfor-mance of the RESURF LDMOSFETS for power ICs. In: Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposiμm on. IEEE, 2009. p. 247-250.
[18] MAO, Kun, et al. A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS. In: Power Semicon-ductor Devices and ICs (ISPSD), 2013 25th International Symposiμm on. IEEE, 2013. p. 397-400.
[19] QIAO, Ming, et al. A 700-V junction-isolated triple RESURF LDMOS with n-type top layer. IEEE Electron Device Letters, 2014, 35.7: 774-776.
[20] QIAO, Ming, et al. A novel substrate termination technology for lateral dou-ble-diffused MOSFET based on curved junction extension. Semiconductor Sci-ence and Technology, 2014, 29.4: 045002.
[21] SU, R. Y., et al. State-of-the-art device in high voltage power ICs with lowest on-state resistance. In: Electron Devices Meeting (IEDM), 2010 IEEE Internation-al. IEEE, 2010. p. 20.8. 1-20.8. 4.
[22] HOSSAIN, Zia, et al. Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance. In: Power Semiconductor Devices and ICs, 2002. Pro-ceedings of the 14th International Symposiμm on. IEEE, 2002. p. 137-140.
[23] TERANISHI, H., et al. A high density, low on-resistance 700V class trench offset drain LDMOSFET (TOD-LDMOS). In: Electron Devices Meeting, 2003. IED-M'03 Technical Digest. IEEE International. IEEE, 2003. p. 31.6. 1-31.6. 4.
[24] LEE, S. H., et al. 700V Lateral DMOS with new source fingertip design. In: Power Semiconductor Devices and IC's, 2008. ISPSD'08. 20th International Symposiμm on. IEEE, 2008. p. 141-144.
[25] SAITO, W., et al. 600V semi-supercon junction MOSFET. In: Power Semicon-ductor Devices and ICs, 2003. Proceedings. ISPSD'03. 2003 IEEE 15th Interna-tional Symposiμm on. IEEE, 2003. p. 45-48.