在下一代無線通信中，通過毫米波頻段來傳輸是解決頻寬資源短缺問題的一個有潛力的方案。且因為毫米波的波長較小，收發器能夠使用大型天線陣列。為了克服毫米波頻段的信號衰減並改善鏈路性能，多輸入多輸出系統採用大天線陣列和預編碼技術。但是，在大型天線陣列中使用的射頻元件會導致硬體成本增高和相當巨大的功耗。基於毫米波射頻元件的高成本與高能耗，近期的研究提出了類比/數位混合式預編碼，作為適用於毫米波多輸入多輸出系統的預編碼架構。此外，混合式粒子濾波器利用通道的時間連續特性來降低在混合預編碼演算法中波束形成的計算複雜度。
本研究依據混合式粒子濾波器的運算性質利用並行多處理元件架構，設計了混合式粒子濾波器演算法的並行硬體架構並提出相應的硬體設計。我們利用QuaDRiGa通道模型來模擬毫米波多輸入多輸出系統並證明並行架構可以在幾乎沒有性能損失的狀況下減少混合式粒子濾波器演算法的計算延遲。最後，我們使用現場可程式化邏輯閘陣列來實現該混合式粒子濾波器的並行多處理元件架構硬體設計，我們設計的處理器可以運作在192 MHz，與研究文獻中的處理器相比，可以減少約73.5%的計算延遲。

In the next generation of wireless communication, the transmission through millimeter wave is a potential solution to the shortage of the bandwidth resources. Due to the small wavelength of millimeter wave, the transceiver is able to use large antenna array. To overcome the signal attenuation of millimeter wave and improved link performance,
the multiple-input multiple-output systems utilized large antenna array and precoding technology. However, the hardware cost and power consumption grows even higher with radio frequency(RF) chains of large antenna array. Hence, the hybrid precoding/ combining scheme is applied to reduce the hardware cost and power consumption. Further more, the mixture framework particle filter, which exploit the temporal continuity of channel, was utilized to reduce the computational complexity of beamforming vector selection of hybrid precoder/combiner reconstruction algorithm.
This study considered the properties of the mixture framework particle filter and utilized parallel multiple-processing element architecture. The corresponding hardware design of the mixture framework particle filter algorithm was proposed with the parallel architecture.
Based on the QuaDRiGa model, the simulation under the 16X16 mmwave MIMO system indicated that the modification of the mixture framework particle filter algorithm reduced the computation latency with negligible performance loss. Finally, the hardware design of the mixture framework particle filter with parallel architecture was
implemented with FPGA. The operating frequency of this hardware design is 192 MHz.

1 Introduction 1
1.1 Millimeter Wave MIMO Systems . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Particle Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Hybrid Precoding and Particle Filter 5
2.1 Precoding in Millimeter Wave MIMO Systems . . . . . . . . . . . . . . . 5
2.1.1 Quadriga Channel Model . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 SVD-Based Precoding Scheme . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Hybrid RF/Baseband Precoding Architecture . . . . . . . . . . . 12
2.2 Hybrid Precoder/Combiner Reconstruction Algorithms . . . . . . . . . . 13
2.2.1 Simultaneous Orthogonal Matching Pursuit (SOMP) . . . . . . . 15
2.2.2 Construction of Candidate Basis Set . . . . . . . . . . . . . . . . 16
2.2.3 Parallel-Index-Selection Matrix-Inversion-Bypass SOMP (PIS-MIBSOMP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Particle Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Sequential Importance Sampling (SIS) Algorithm . . . . . . . . . 20
2.3.3 Sequential Importance Resampling (SIR) Particle Filter . . . . . . 22
3 Index-Selection Using Multiple-PE Particle Filter in PIS-MIB-SOMP 27
3.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 Weighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Distribution calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.6 Successive Interference Cancellation (SIC) Estimation . . . . . . . . . . . 41
3.7 Simplified Resampling Algorithm with Non-Normalized Weights . . . . . 44
3.8 Simulation Result and Analysis . . . . . . . . . . . . . . . . . . . . . . . 48
3.8.1 Simulation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.8.2 Simulation of Internal Parameters . . . . . . . . . . . . . . . . . . 51
3.8.3 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . 57
4 Architecture Design 63
4.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.1.1 Architecture of PE . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.1.2 Architecture of CU . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.1.3 Timing Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 Fixed-point Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.3 FPGA verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4 FPGA Synthesis Result . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5 Conclusion 79

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