本文主要致力於研究4H-碳化矽功率場效金氧半電晶體特性的改善，從以下幾個面向著手：導電性能、耐壓能力以及積體化集成的潛力。首先，碳化矽金氧半場效電晶體有著先天的高通道電阻特性，來自於氧化後於二氧化矽與碳化矽介面產生大量的缺陷，為了改善這個問題，我們引入矽離子表面佈植技術。其次，碳化矽功率元件的耐壓能力，受到反向操作時元件邊緣電場集中的影響，無法達到理想耐壓，為了改善元件耐壓能力，我們發展新的邊緣保護技術，並使用在3300伏等級的碳化矽垂直型電晶體上。此外，此種邊緣保護技術可以容忍元件表面正電荷變化的影響，對於伽瑪射線有一定的防護能力，我們也對此做了實驗測試。最後，對了實現碳化矽控制電路與垂直型耐壓電晶體可以積體化於同一個晶片上，我們採用商用碳化矽金氧半電晶體的製程，在不使用多於的光罩與製程下，嘗試製作碳化矽互補式金氧化半電晶體，並研究與垂直型電晶體聯動操作的可能性。
本研究主要達成之成果為:
1. 使用矽離子表面佈植技術，改善碳化矽場效電晶體通道電子遷移率5%，進而提升導通能力，並於可靠度驗證上略優於沒有採用此方法的對照組。
2. 發展反摻雜接面終結延伸的邊緣保護技術，並應用於3300伏等級的碳化矽垂直性電晶體上，達到最高耐壓4100伏(模擬理論值的95%)。
3. 前述反摻雜接面終結延深保護的3300伏等級的碳化矽垂直形電晶體，在伽瑪射線耐受度實驗上，於累積照射劑量700 kGy照射後，仍然可以正常操作，特性遠勝於矽絕緣柵雙極電晶體(IGBT)。
4. 首次展示碳化矽互補式金氧半電晶體與垂直型功率電晶體的積體化，並研究垂直型功率電晶體操作對於邏輯閘反向器的影響。

This thesis is mainly devoted to the research on the improvement of the characteristics of 4H-silicon carbide (SiC) power MOSFETs, starting from the following aspects: conduction performance, blocking capability and the potentiality of integration. First of all, SiC MOSFETs have inherent high channel resistance characteristics, which comes from a large number of defects in the SiO2 and SiC interface after oxidation process. In order to improve this problem, we introduce a Si implanted surface treatment technique. Secondly, the blocking capability of SiC power devices is affected by the crowding of electric field at edge corner of device during reverse bias, and thus the ideal breakdown voltage cannot be achieved. In order to improve the blocking capability of devices, we develop a new edge termination technique and apply it on 3.3 kV class SiC vertical MOSFETs (VDMOS). In addition, this edge termination technique can also provide tolerance of positive charge variation on the surface of the devices, and has a certain degree of protection against gamma rays. We have also made experimental tests to examine on this property. Finally, to realize that the control circuits and the vertical power device can be integrated on the same SiC chip, we use the commercial SiC VDMOS processes without additional masks and processes, trying to make SiC complementary metal-oxide-semiconductor (CMOS) and survey the possibility of interaction with VDMOS.

The main results of this thesis are listed as the following:
1. Applying Si implanted surface treatment technique on SiC MOSFETs to improve their electron mobility and achieving 5% improvement of channel mobility, thereby increasing the conduction capability. Furthermore, among the reliability tests, Si-implanted devices are slightly better than the non-Si implanted group.
2. Developing a new edge termination of counter-doped junction termination extension (CD-JTE), and applying it to the 3.3 kV class SiC VDMOS. The maximum breakdown voltage is 4100 V (95% of the simulated theoretical value).
3. The aforementioned 3.3 kV class SiC VDMOS guarding with CD-JTE can still normally operate after being irradiated with an accumulative radiation dose of 700 kGy in the gamma-ray tolerance test, and is superior to Si insulated gate bipolar transistor (IGBT).
4. Demonstration the integration of SiC CMOS and vertical power device for the first time, and studying the effect on SiC logic gate of inverter as vertical power transistor operation.

Abstract
Contents
Chapter 1. Introduction 1
1.1 Wide Bandgap (WBG) Material - Silicon Carbide (SiC) 1
1.2 Power MOSFETs 2
1.3 Improvement Applied on SiC Power MOSFETs 3
1.3.1 Improvement in Forward Conduction 3
1.3.2 Improvement in Breakdown Voltage 4
1.4 Radiation Hardening of Gamma-ray Irradiation 5
1.5 Reliability 6
1.6 SiC CMOS Integration Circuits 7
Chapter 2. Improvement in Forward Conduction of SiC MOSFETs 13
2.1 Si-implanted Surface Treatment 13
2.1.1 DC Characteristics of Lateral MOSFETs 14
2.1.2 VTH Roll Off of Lateral MOSFETs 15
2.1.3 Dielectric Properties Affected by Si implantation 16
2.1.4 Minority Carrier Lifetime 16
2.1.5 Temperature coefficient of Si implanted MOSFETs 17
2.1.6 DC Characteristics of Si implanted VDMOS 17
2.2 Reliabilty Examination of Si-implanted SiC MOSFETs 34
2.2.1 Reliability Evaluation in Low Voltage MOSFETs 34
2.2.2 Reliability Evaluation in High Voltage VDMOS 35
2.3 On the Effect of Impact Ionization Occurring in Gate Oxide of SiC MOS Devices 44
2.3.1 Constant Voltage Stress at High Gate Voltage 44
2.3.2 Impact Ionization Boundary and The Limit of Operation Voltage 46
Chapter 3. Improvement in Breakdown Voltage of SiC MOSFETs 52
3.1 CD-JTE Termination for 4H-SiC Power Devices 52
3.1.1 Device Design and Fabrication 52
3.1.2 Experimental Results and Discussion 53
3.2 Implementation of CD-JTE Termination on 3.3 kV Class SiC VDMOS 59
Chapter 4. Radiation Hardening of Gamma-ray Irradiation Investigate on 4H-SiC Power MOSFETs 64
4.1 Radiation Hardening of Gamma-ray on SiC Commercial Power MOSFETs 64
4.1.1 Irradiation Procedure and Experiment Results 64
4.1.2 The Effect of Direction on the Irradiation Gamma-ray 67
4.2 Gamma-ray radiation examination on 3.3 KV class SiC CD-JTE VDMOS 76
4.2.1 Device Structure and Experimental Details 76
4.2.2 Results and Discussion 76
Chapter 5. SiC CMOS Implementation Using Commercial VDMOS Process for the Integration of SiC Discrete Device and Control Circuit 86
5.1 Device Structure and Experiment Results 86
5.2 Effects from Substrate Bias 88
Chapter 6. Conclusion and Future Work 96
Reference 100
附錄 108

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