本論文主要利用TCAD模擬探討Superjunction MOSFET的主動區與邊緣終端區在不同Charge Imbalance的條件下的特性與未箝制電感切換(UIS)的性能。在多層磊晶堆疊技術製程下利用調整離子佈植劑量的方式達到Charge Imbalance的條件，在不同離子佈植劑量比下，由於邊緣終端區中的過渡區為Superjunction結構，故反向特性上主動區與邊緣終端區皆受Charge Imbalance影響，主動區最高崩潰電壓在劑量比為5%的時候，而邊緣終端區最高崩潰電壓在劑量比為0%的時候，比較兩者的崩潰電壓關係後，元件最佳的Charge Balance條件在劑量比為0%。
UIS測試的模擬是透過Mixed-mode來執行，針對元件發生失效時所受的雪崩能量進行，並且討論雪崩電流路徑的分布、失效的機制和破壞點位置。模擬結果顯示在P柱離子佈植劑量較多的情況下元件的EAS值較佳，而在每一種Charge Imbalance條件下，從元件失效時雪崩電流與溫度的最高處來判斷，六種條件之元件破壞點皆在主動區，並且從電子流密度分布與源極電子流大小可知失效的機制皆源於觸發寄生雙極性電晶體。

The main objective of this thesis is the simulation study for the performance of Superjunction MOSFET including cell and edge termination under different charge imbalance conditions, as well as the ruggedness under Unclamped Inductive Switching (UIS). The condition of charge imbalance is achieved by adjusting the ion implantation dose in a typical epi-implant approach to form p- and n- columns. At different ion implantation dose ratios, since the transition region in the edge termination is a superjunction-like structure. Therefore both the reverse characteristics of cell and edge termination are influenced by charge imbalance. When the dose ratio is 5%, the breakdown voltage in the cell region is maximized, and when the dose ratio is 0%, the breakdown voltage in the edge termination is maximized. After comparing the relationship between the breakdown voltage in the cell region and edge termination, the optimized charge imbalance condition of device is 0%.
Then, the UIS test is simulated using mixed-mode. The avalanche energy (EAS) at which the device fails to turn off is examined, and the distribution of the avalanche current path, the mechanism of failure, and the location of the failure point is discussed. The simulation results show that EAS value is better in the case of p-column richer in dosage. In each of the charge imbalance conditions, by looking at the highest avalanche current value and temperature when the device fails, it is concluded that the failure point is located in the cell region, and the mechanism of failure is attributed to the triggering of parasitic bipolar transistors.

中文摘要 I
Abstract II
致謝 III
目錄 V
圖目錄 VII
表目錄 XI
第一章 序論 1
1.1 研究動機 2
1.2 論文大綱 3
1.3文獻回顧 3
1.3.1 元件基本原理 3
1.3.2 未箝制電感切換 6
1.3.3 未箝制電感切換失效機制 9
第二章 元件結構與反向耐壓模擬 27
2.1 元件結構模擬 27
2.2 靜態電性模擬 28
第三章 未箝制電感切換模擬 41
3.1 MIXED-MODE介紹 41
3.2 模擬結果 41
3.3 破壞點位置與失效機制分析 44
第四章 結論與未來展望 59
參考文獻 61

[1] B. J. Baliga, Fundamentals of Power Semiconductor Devices, NY: Springer, 2008.
[2] D. J. Coe, “High voltage semiconductor device,” U.S. Patent 4 754 310, Jun. 28, 1988.
[3] X. Chen, “Semiconductor power devices with alternating conductivity
type high-voltage breakdown regions,” U.S. Patent 5 216 275, Jun. 1, 1993.
[4] T. Fujihira, “Theory of semiconductor superjunction devices,” Jpn. J. Appl. Phys., vol. 36, pp. 6254-6262, 1997.
[5] L. Lorenz, G. Deboy, A. Knapp and M. Marz, “CoolMOS™ - A new milestone in high voltage power MOS,” In Proc. ISPSD'99 1999, 1999.
[6] G. Deboy, N. Marz, J. -. Stengl, H. Strack, J. Tihanyi and H. Weber, “A new generation of high voltage MOSFETs breaks the limit line of silicon,” International Electron Devices Meeting 1998. Technical Digest, 1998, pp. 683-685.
[7] Y. C. Liang and G. S. Samudra, Power Microelectronics: Device and Process Technologies, Hackensack: World Scientific Publishing, 2009.
[8] K. Sano et al., “Small current unclamped inductive switching (UIS) to detect fabrication defect for mass-production phase IGBT,” 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018, pp. 116-119.
[9] S. Soneda et al., “Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition,” 2012 24th International Symposium on Power Semiconductor Devices and ICs, 2012, pp. 153-156.
[10] VISHAY SILICONIX, Appl. Note 849, pp.1-5.
[11] P. N. Kondekar, C. D. Parikh and M. B. Patil, “Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer,” 2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference. Proceedings, 2002, pp. 1769-1775.
[12] P. M. Shenoy, A. Bhalla and G. M. Dolny, “Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET,” 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312), 1999, pp. 99-102.
[13] M. Bobde, L. Guan, A. Bhalla, F. Wang and M. Ho, “Analyzing Super-Junction C-V to estimate charge imbalance,” 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, pp. 321-324.
[14] Renesas Electronics Corporation, Appl. Note 1968, pp.1-6.
[15]L. Jiang, T. Xiaoli, L. Shuojin, Z. Hongyu, Z. Yangjun, H. Zhengsheng, “Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions,” Journal of Semiconductors, vol. 34, no. 3, pp. 26-30, 2013.
[16] R. R. Stoltenburg, "Boundary of power-MOSFET, unclamped inductive-switching (UIS), avalanche-current capability," Proceedings, Fourth Annual IEEE Applied Power Electronics Conference and Exposition, Baltimore, 1989, pp. 359-364.
[17] Infineon Technologies, Appl. Note 1005, pp.1-17.
[18] M. Ren, Z. H. Li, G. M. Deng, L. X. Zhang, M. Zhang, X. L. Liu, J. X. Xie, B. Zhang, “A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching,” Chin. Phys. B 2012, 21 (4): 048502.
[19] L. Jiang, W. Lixin, L. Shuojin, W. Xuesheng, H. Zhengsheng, “Avalanche behavior of power MOSFETs under different temperature conditions,” Journal of Semiconductors, vol. 32, pp. 014001, 2011.
[20] A. Icaza Deckelmann, G. Wachutka, F. Hirler, J. Krumrey: “UIS- Failure of DMOS Power Transistors,” Proc. of the 32nd European Solid-State Research Conference (ESSDERC) 2002, pp. 459-462.
[21] A.lzaca Decke1mann, G. Wachutka, F. Hirler, 1. Krumrey, and R. Henninger, “Failure of Multiple-Cell Power DMOS Transistor in Avalanche Operation,” Proc. of the 33'd European Solid State Research, pp. 323-326.
[22] J. Rhayem, A. Wieers, A. Vrbicky, P. Moens, A. Villamor-Baliarda, J. Roig, P. Vanmeerbeek, A. Irace, M. Riccio, M. Tack, “Novel 3D electro-thermal robustness optimization approach of super junction power MOSFETs under unclamped inductive switching,” Proc. 28th Annu. IEEE Semiconductor Thermal Measurement and Management Symp. (SEMI-THERM), pp. 68-73.
[23] G. A. M. Hurkx and N. Koper, “A physics-based model for the avalanche ruggedness of power diodes,” 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings, 1999, pp. 169-172.

[24] H. Egawa, “Avalanche characteristics and failure mechanism of high voltage diodes,” in IEEE Transactions on Electron Devices, vol. ED-13, no. 11, pp. 754-758, Nov. 1966.
[25] A. Villamor Baliarda, “Avalanche Ruggedness of Local Charge Balance Power Super Junction Transistors,” PhD. Dissertation, Universitat Autònoma de Barcelona, 2013
[26] W. Saito et al., “A 20mΩcm2 600 V-class Superjunction MOSFET,” in Proc. ISPSD, May 2004, pp. 459–462.
[27] A. Villamor Baliarda et al., “Influence of charge balance on the robustness of trench-based super junction diodes,” Microelectron. Rel., vol. 52, no. 9–10, pp. 2409-2413, 2012.
[28] G. Deboy et al., “Power Semiconductor compensation structure and method for producing the same,” US Patent No. 7646061 B2(2010)
[29] S. Sridevan, “Superjunciton device with improved ruggedness”, US Patent No. 7,166,890 B2, 2007.
[30] 任敏 et al., “一種具有優化雪崩擊穿電流路徑的超結MOSFET器件,” CN 102832245A, 2011.
[31] C. K. Kim, J. M. Geum, and Y. T. Kim, “Effects of Charge Imbalance on Super Junction Power MOSFET,” Recent Advances in Telecommunications and Circuits, pp.27-30
[32] F. Stückler, “Next-generation SJ MOSFETs extend performance of silicon-based power devices,” July 05, 2013. [Online]. Available: https://www.powersystemsdesign.com/articles/next-generation-sj-mosfets-extend-performance-of-silicon-based-power-devices/22/5914.
[33] P. N. Kondekar, H. S. Oh, Y. B. Cho and Y. B. Kim, “The effect of static charge imbalance on the on state behavior of the superjunction power MOSFET: CoolMOS,” The Fifth International Conference on Power Electronics and Drive Systems 2003, Singapore, 2003, pp. 77-80.
[34] H. Yamashita et al., “Suppression of switching loss dependence on charge imbalance of superjunction MOSFET,” 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015, pp. 405-408.
[35] M. Yasushi et al., “Semiconductor device with alternating conductivity type layer and method of manufacturing the same,” US Patent No. 6291856B1, 2001.
[36] Synopsys, Sentaurus™ Process User Guide Version L-2016.03, March 2016.
[37] Synopsys, Sentaurus™ Device User Guide Version L-2016.03, March 2016.