碳化矽金氧半場效電晶體的場效電子遷移率過低一直以來是碳化矽元件最大的缺點，在文獻中透過氧化後進行二氧化氮熱退火可以讓通道遷移率有效提升。本論文研究矽離子佈植氧化製程對碳化矽金氧半場效電晶體特性影響。
本論文利用現有的4H碳化矽垂直型雙佈直金氧半場效電晶體製程技術整合4H碳化矽水平型金氧半場效電晶體；將氧化後二氧化氮(N2O) 退火及矽離子佈植等應用於碳化矽金氧半場效電晶體之設計，將順向特性之優化。在順向特性上，藉由調整不同的矽離子佈植的劑量等參數，可以將介面缺陷密度(Dit)及通道遷移率之優化。在逆向方面則是來探討矽離子佈植是否會對元件有負面影響。實驗結果發現Si離子佈植將水平型SiC NMOS的通道電子遷移率由原本的18cm2/V∙s 提升至19cm2/V∙s，平均介面缺陷密度也有所下降；而垂直型DMOS其Ron,sp則由5.27mΩ ∙cm2降至4.22mΩ∙cm2，Id,sat也獲得了一定程度的放大。

Low inversion channel mobility is one of the main challenges of current SiC MOSFETs. Post-oxidation annealing in N2O has been developed to enhance the mobility in previous studies. In this study, we investigate the effect of Si implantation oxidation process on the performance of 4H-SiC MOSFETs
This study uses a standard 4H-SiC DMOS process to make 4H-SiC lateral MOSFETs. This study investigates the design of Post-oxidation annealing in N2O and Si-implanted for 4H-SiC MOSFET and the optimization of its forward characteristics. In forward characteristics, by adjusting Si-implant parameters, the interface trap density (Dit) and channel mobility can be improved. In reverse characteristics, the experimental results show that Si-implant has nearly no effect on the breakdown voltage and leakage current. Compared to the sample without pre-oxidation process, the field effect mobility is increased from 18.01 cm^2/V∙s to 19.10 cm^2/V∙s, and the Dit is also reduced. Besides , Ron,sp of DMOS is also reduced from 5.27mΩ〖 ∙cm〗^2 ,and the saturation current is also increased.

中文摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VIII
第一章 序論 1
1.1 碳化矽(SiC)材料簡介 1
1.1.2 碳化矽材料組成 2
1.2文獻回顧 3
1.2.1 氧化後退火提升通道電子遷移率 3
1.2.2 氧化前離子佈植 4
1.3 研究動機與論文大綱 5
第二章 元件設計及實驗介紹 7
2.1元件設計 7
2.1.1 垂直型電容器 7
2.1.2 水平型金氧半場效電晶體(Lateral MOSFET)介紹 8
2.1.3 垂直型雙佈植金氧半場效電晶體 19
2.2 試片分配 20
2.3元件量測介紹 24
2.3.1 Ho-lo CV 24
2.3.2 電荷汲引(Charge-Pumping) 25
第三章 實驗數據整理討論 30
3.1 WAT (electric test)測結果 30
3.1.1 epi-layer 濃度/厚度量測 30
3.1.2 歐姆接觸量測 32
3.2 垂直電容量測及討論 37
3.3 水平金氧半場效電晶體量測及討論 42
3.3.1 順向電流量測 42
3.3.2 電荷汲引量測 50
3.4 垂直型雙佈植金氧半場效電晶體量測 53
第四章 結論以及未來展望 57
參考文獻 58

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